DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 1 is objected to because of the following informalities:
After” A display substrate, comprising”, missing “:”.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-15 & 17-21 is/are rejected under 35 U.S.C. 102(A)(2) as being anticipated by Bang et al. (US 20220149140).
Regarding claim 1, Bang discloses that a display substrate 100, comprising a display area (Fig. 3 & 4), a side bezel region PA1 located on at least one side of the display area in a first direction, and a bonding area 14 located on a side of the display area DA in a second direction, wherein the side bezel region at least comprises a first bezel region and a second bezel region, the first bezel region is located on a side of the second bezel region close to the bonding area, and the first direction intersects the second direction (Fig. 3 & 4);
the display substrate 14 comprises a base substrate and a drive circuit layer provided on the base substrate (Fig. 5 & 15), the base substrate 100 at least comprises a first connection line, the drive circuit layer at least comprises a data signal line DLx and a second connection line DV`x, the second connection line is connected to the first connection line DHx & DVx through a first lap via DH-CNT2, the data signal line DLx is connected to the second connection line DV1x through a second lap via CNT3, and the first lap via is provided in the first bezel region (Fig. 5).
Reclaim 2, Bang discloses that the display substrate comprises a first center line DLx that is a straight line bisecting the display area in the second direction and extending in the first direction, the first bezel region is located on a side of the first center line close to the bonding area, and the first connection line and the second connection line are located on a side of the first center line close to the bonding area (Fig. 3, 5, & 15).
Reclaim 3, Bang discloses that the display substrate comprises a second center line DLx that is a straight line bisecting the display area in the first direction and extending in the second direction; distances between a plurality of second lap vias and the second center line are gradually increased in a direction away from the first center line, and distances between the plurality of second lap vias and the first center line are gradually increased in a direction away from the second center line; or, distances between the plurality of second lap vias and the second center line are gradually reduced in a direction away from the first center line, and distances between the plurality of second lap vias and the first center line are gradually reduced in a direction away from the second center line(Fig. 3, 5, & 15).
Reclaim 4, Bang discloses that the bonding area at least comprises a lead line, a first end of the lead line is correspondingly connected to an integrated circuit in the bonding area, a second end of the lead line is correspondingly connected to a first end of the first connection line, a second end of the first connection line is connected to a first end of the second connection line through the first lap via after extending from the bonding area to the first bezel region through the display area, a second end of the second connection line is connected to the data signal line through the second lap via after extending from the first bezel region to the display area (Fig. 3, 5, & 15).
Reclaim 5, Bang discloses that the side bezel region comprises an encapsulation region and a non-encapsulation region that are divided by an encapsulation line, the encapsulation line is a boundary of an encapsulation structure layer covering the side bezel region, the encapsulation region is provided on a side of the encapsulation line close to the display area, the non-encapsulation region is provided on a side of the encapsulation line away from the display area, and the first lap via is provided in the non-encapsulation region (Fig. 3, 5, & 15).
Reclaim 6, Bang discloses that the drive circuit layer at least comprises a first conductive layer, a second conductive layer and a third conductive layer that are sequentially provided on the base substrate, the second connection line is provided in the first conductive layer or the second conductive layer, and the data signal line is provided in the third conductive layer (Fig. 15).
Reclaim 7, Bang discloses that the first connection line comprises at least a first sub-line and a second sub-line, a first end of the second sub-line is connected to a lead line of the bonding area, a second end of the second sub-line is connected to a first end of the first sub-line after extending to the display area in the second direction, and a second end of the first sub-line is connected to a first end of the second connection line through the first lap via after extending to the first bezel region in the first direction (Fig. 3 & 5).
Reclaim 8, Bang discloses that in the display area, for a first sub-line and a second connection line that transmit the same data signal, an orthographic projection of the first sub-line on the base substrate at least partially overlaps with an orthographic projection of the second connection line on the base substrate (Fig. 3 & 5).
Reclaim 9, Bang discloses that in the second direction, extension lengths of a plurality of second connection lines are gradually increased or extension lengths of the second connection lines are gradually reduced (Fig. 3 & 5).
Reclaim 10, Bang discloses that the drive circuit layer comprises circuit units constituting a plurality of unit rows and a plurality of unit columns, at least one circuit unit comprises a pixel drive circuit, at least one pixel drive circuit comprises a storage capacitor and a plurality of transistors, and orthographic projections of the first connection line and the second connection line on the base substrate do not overlap with orthographic projections of the storage capacitor and the plurality of transistors on the base substrate (Fig. 3 & 5).
Reclaim 11, Bang discloses that the display substrate comprises a plurality of lead groups, at least one lead group comprises k first sub-lines, and k second connection lines correspondingly connected to the k first sub-lines through k first lap vias, the k second connection lines are correspondingly connected to k data signal lines through k second lap vias, and k is a positive integer greater than or equal to 1; and in the display area, at least one lead group is provided between adjacent unit rows (Fig. 3 & 5).
Reclaim 12, Bang discloses that in the second direction, a distance between an i-th lead group and an (i+1)-th lead group is equal to a distance between the (i+1)-th lead group and an (i+2)-th lead group, i is a positive integer greater than or equal to 1, and less than or equal to N-2, and N is a quantity of the lead groups (Fig. 3 & 5).
Reclaim 13. (Original) The display substrate according to claim 12, wherein k is 2, and a spacing between two second lap vias in the i-th lead group is equal to a spacing between two second lap vias in the (i+1)-th lead group (Fig. 3 & 5).
Reclaim 14, Bang discloses that the side bezel region at least comprises a gate circuit region, the gate circuit region comprises a plurality of gate circuit groups sequentially provided in the second direction, a trace region is provided between adjacent gate circuit groups, and at least one lead group is provided in the trace region in the side bezel region; at least one gate circuit group comprises m scan gate circuits sequentially provided in the second direction and n light emitting gate circuits sequentially provided in the second direction, the n light emitting gate circuits are provided on a side of the m scan gate circuits away from the display area, m is a positive integer greater than or equal to 2, and n is a positive integer greater than or equal to 1 (Fig. 3 & 5).
Reclaim 15, Bang discloses that at least one scan gate circuit comprises a plurality of scan transistors and a scan storage capacitor, at least one light emitting gate circuit comprises a plurality of light emitting transistors and a light emitting storage capacitor, and in at least one lead group, orthographic projections of the first sub-line and the second connection line on the base substrate do not overlap with orthographic projections of the scan transistor, the scan storage capacitor, the light emitting transistor and the light emitting storage capacitor on the base substrate:-_ or wherein the gate circuit region further comprises at least one start signal line and at least one clock signal line that extend in the second direction, and in at least one lead group, orthographic projections of the first sub-line and the second connection line on the base substrate have a first overlapping area with orthographic projections of the start signal line and the clock signal line on the base substrate (Fig. 3 & 5).
Reclaim 17, Bang discloses that in the first overlapping area, an orthographic projection of the first sub-line on the base substrate does not overlap with an orthographic projection of the second connection line on the base substrate (Fig. 3 & 5).
Reclaim 18, Bang discloses that in a side bezel region other than the first overlapping area, for a first sub-line and a second connection line that transmit the same data signal, an orthographic projection of the first sub-line on the base substrate at least partially overlaps with an orthographic projection of the second connection line on the base substrate.
Reclaim 19, Bang disclose that at least one first sub-line or at least one second connection line is provided with a resistance compensation structure provided on a side of the gate circuit region away from the display area (Fig. 3 & 5).
Reclaim 20, Bang discloses that a display device, comprising a display substrate according to claim 1.
Reclaim 21, Bang discloses that a method for preparing a display substrate, wherein the display substrate comprises a display area, a side bezel region located on at least one side of the display area in a first direction, and a bonding area located on a side of the display area in a second direction, wherein the side bezel region at least comprises a first bezel region and a second bezel region, the first bezel region is located on a side of the second bezel region close to the bonding area, and the first direction intersects the second direction; and the method comprises: forming a base substrate at least comprising a first connection line; and forming a drive circuit layer on the base substrate, wherein the drive circuit layer at least comprises a data signal line and a second connection line, the second connection line is connected to the first connection line through a first lap via, the data signal line is connected to the second connection line through a second lap via, and the first lap via is provided in the first bezel region (See rejected claim 1).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SU C KIM whose telephone number is (571)272-5972. The examiner can normally be reached M-F 9:00 to 5:00.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dale Page can be reached at 571-270-7877. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/SU C KIM/ Primary Examiner, Art Unit 2899
Prosecution Insights