DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claims 11, 13-16 and 18-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 11, 13-16, 18 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US PGPUB 2019/0049510) in views of Barr et al. (US Pat. 6,940,288) and CLARKSON (US PGPUB 2012/0217976).
Regarding claim 11, Lee et al. teaches an electronic control unit (100), comprising: a printed circuit board (PCB, as shown in fig. 1); a package including an electronic circuit (as disclosed in para. 0017), wherein the package is arranged on the printed circuit board and electrically coupled to the printed circuit board (as disclosed in para. 0017); at least one analog-to-digital converter (ADC0-ADC3) which is electrically coupled to at least one of the solder joints (NCTF VSS Balls) and is configured to generate a measurement signal based on an electrical resistance of the at least one electrically coupled solder joint (NCTF VSS Balls) (as disclosed in para. 0023); and an external resistance (provided as part of the voltage divider 101, as shown in fig. 1), to which a reference potential (VREF) is applied (as disclosed in para. 0023), wherein the external resistance is connected in series with the electrical resistance of the at least one of the solder joints (NCTF VSS Balls) to provide a voltage divider (as shown in fig. 1 and disclosed as voltage divider 101).
Lee et al. fails to specifically teach wherein, using a plurality of solder joints, the package is arranged on the printed circuit board and electrically coupled to the printed circuit board. However, Barr et al. teaches wherein, using a plurality of solder joints (20), the package (14) is arranged on the printed circuit board (12) and electrically coupled to the printed circuit board (12) (as shown in fig. 1 and disclosed in col. 3, lines 6-45).
It would have been obvious, before the effective filing date of the claimed invention, to one of ordinary skill in the art to combine and have using a plurality of solder joints, the package arranged on the printed circuit board and electrically coupled to the printed circuit board as taught by Barr et al. with the invention of Lee et al. in order to securely and accurately positioning the package for inspection.
The combination of Lee et al. and Barr et al. fails to specifically teach a current limiting resistance having a first terminal connected to a node disposed on a line connecting the external resistance in series with the electrical resistance of the at least one of the solder joints. However, CLARKSON teaches a current limiting resistance (213) having a first terminal connected to a node disposed on a line (209) connecting the external resistance (203) in series with the electrical resistance of the at least one of the solder joints (201’) (as shown in fig. 3).
It would have been obvious, before the effective filing date of the claimed invention, to one of ordinary skill in the art to combine and have a current limiting resistance having a first terminal connected to a node disposed on a line connecting the external resistance in series with the electrical resistance of the at least one of the solder joints as taught by CLARKSON with the invention of the combination of Lee et al. and Barr et al. in order to improve detection of failed solder joints at the expense of increased power consumption (CLARKSON para. 0037).
Regarding claim 13, the combination of Lee et al., Barr et al. and CLARKSON teaches the limitations of claim 11, in addition, Lee et al. teaches an evaluation device (102) configured to calculate a quality of the at least one of the solder joints based on the measurement signal (as disclosed in para. 0023).
Regarding claim 14, the combination of Lee et al., Barr et al. and CLARKSON teaches the limitations of claim 13, in addition, Lee et al. teaches wherein the evaluation device calculates the quality based on an at least three-stage scale (good, marginal or failed state, as disclosed in para. 0019-0021).
Regarding claim 15, the combination of Lee et al., Barr et al. and CLARKSON teaches the limitations of claim 11, in addition, Lee et al. teaches wherein the plurality of solder joints are solder balls (NCTF VSS Balls) or solder pins (as shown in fig. 1).
Regarding claim 16, the combination of Lee et al., Barr et al. and CLARKSON teaches the limitations of claim 11, in addition, Lee et al. teaches wherein the plurality of solder joints is arranged on a rectangular base (rectangular base formed by PCB, as shown in fig. 1), and wherein the at least one analog-to-digital converter (ADC0-ADC3) is electrically coupled to at least one of the solder joints (NCTF VSS Balls) in a corner of the rectangular base (as shown in fig. 1).
Regarding claim 18, the combination of Lee et al., Barr et al. and CLARKSON teaches the limitations of claim 11, in addition, Barr et al. teaches wherein the electronic circuit (14) is a microcontroller or an application-specific circuit (ASIC).
It would have been obvious, before the effective filing date of the claimed invention, to one of ordinary skill in the art to combine and have the electronic circuit as an application-specific circuit (ASIC) as taught by Barr et al. with the invention of the combination of Lee et al., Barr et al. and CLARKSON in order to use a device with lower power consumption and reduced size.
Regarding claim 20, Lee et al. teaches a method for monitoring at least one solder joint of an electronic control unit (100), wherein the electronic control unit (100) includes a printed circuit board (PCB, as shown in fig. 1) and a package having an electronic circuit (as disclosed in para. 0017), and wherein at least one analog-to-digital converter (ADC0-ADC3) is electrically coupled to at least one of the solder joints (NCTF VSS Balls), wherein the method comprises the following steps: generating (as disclosed in para. 0023), using the at least one analog-to-digital converter (ADC0-ADC3), a measurement signal based on an electrical resistance of the at least one of the solder joints electrically coupled to the analog-to-digital converter (as disclosed in para. 0023); and outputting the generated measurement signal (as disclosed in para. 0023), wherein: and an external resistance (provided as part of the voltage divider 101, as shown in fig. 1), to which a reference potential (VREF) is applied (as disclosed in para. 0023), wherein the external resistance is connected in series with the electrical resistance of the at least one of the solder joints (NCTF VSS Balls) to provide a voltage divider (as shown in fig. 1 and disclosed as voltage divider 101).
Lee et al. fails to specifically teach wherein, using a plurality of solder joints, the package is arranged on the printed circuit board and electrically coupled to the printed circuit board. However, Barr et al. teaches wherein, using a plurality of solder joints (20), the package (14) is arranged on the printed circuit board (12) and electrically coupled to the printed circuit board (12) (as shown in fig. 1 and disclosed in col. 3, lines 6-45).
It would have been obvious, before the effective filing date of the claimed invention, to one of ordinary skill in the art to combine and have using a plurality of solder joints, the package arranged on the printed circuit board and electrically coupled to the printed circuit board as taught by Barr et al. with the invention of Lee et al. in order to securely and accurately positioning the package for inspection.
The combination of Lee et al. and Barr et al. fails to specifically teach a first terminal of a current limiting resistance is connected to a node disposed on a line connecting the external resistance in series with the electrical resistance of the at least one of the solder joints. However, CLARKSON teaches a first terminal of a current limiting resistance (213) is connected to a node disposed on a line (209) connecting the external resistance (203) in series with the electrical resistance of the at least one of the solder joints (201’) (as shown in fig. 3).
It would have been obvious, before the effective filing date of the claimed invention, to one of ordinary skill in the art to combine and have a first terminal of a current limiting resistance connected to a node disposed on a line connecting the external resistance in series with the electrical resistance of the at least one of the solder joints as taught by CLARKSON with the invention of the combination of Lee et al. and Barr et al. in order to improve detection of failed solder joints at the expense of increased power consumption (CLARKSON para. 0037).
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US PGPUB 2019/0049510), Barr et al. (US Pat. 6,940,288) and CLARKSON (US PGPUB 2012/0217976) as applied to claim 11 above, and further in view of Cejka et al. (US Pat. 9,377,504).
Regarding claim 19, the combination of Lee et al., Barr et al. and CLARKSON teaches the limitations of claim 11.
The combination of Lee et al., Barr et al. and CLARKSON fails to specifically teach wherein the electronic circuit is connected to the plurality of solder joints via an interposer. However, Cejka et al. teaches wherein the electronic circuit (110) is connected to the plurality of solder joints via an interposer (120) (as shown in fig. 1 and disclosed in col. 2, lines 34-54).
It would have been obvious, before the effective filing date of the claimed invention, to one of ordinary skill in the art to combine and have the electronic circuit connected to the plurality of solder joints via an interposer as taught by Cejka et al. with the invention of the combination of Lee et al., Barr et al. and CLARKSON in order to provide a structural foundation for the package and for communicating signals between external and internal circuits.
Allowable Subject Matter
Claims 21-22 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ROBERTO VELEZ whose telephone number is (571)272-8597. The examiner can normally be reached Mon-Fri 5:30am-3:30pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Huy Phan can be reached at (571)272-7924. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ROBERTO VELEZ/Primary Examiner, Art Unit 2858