DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-3, 13, & 20-21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ma (US 20180090071).
Regarding claim 1, Ma discloses that an array substrate, comprising a plurality of first gate lines, a plurality of second gate lines, and a plurality of pixel driving circuits;
wherein a respective pixel driving circuit of the plurality of pixel driving circuits comprises a driving transistor, a data write transistor DTFT, a compensating transistor T3, a storage capacitor, a first node A connecting line connecting a gate electrode of the driving transistor DTFT with a first electrode of the compensating transistor T3;
a respective A-DTFT first gate line of the plurality of first gate lines configured to provide a gate scanning signal Ref2 to the data write transistor DTFT;
a respective second gate line of the plurality of second gate lines configured to provide a gate scanning signal Ref2 to the compensating transistor T3 (Fig. 2);
wherein the array substrate comprises a first semiconductor material layer and a second semiconductor material layer on a side of the first semiconductor material layer away from a base substrate (stack of semiconductor material on a substrate);
the first semiconductor material layer comprises at least active layers of the driving transistor T1 pr T2 and the data write transistor DTFT (a channel of the driving transistor and the data wiring transistor);
the second semiconductor material layer comprises at least an active layer of the compensating transistor T3 (channel of T3);
a first parasitic capacitor C1 is formed between the second semiconductor material layer Tc and the respective first gate line A-DTFT (Fig. 2);
a second parasitic capacitor C1 is formed between the first node connecting line and the respective second gate line A-B-T3 (Fig. 2).
Ma fail to specify that a ratio of a capacitance of the first parasitic capacitor to a capacitance of the second parasitic capacitor is greater than 2.3.
However, notwithstanding, one of ordinary skill in the art would have been led to the recited dimensions through routine experimentation and optimization.
Before effective filing date of the invention it would have been obvious to a person of ordinary skill in the art to use a certain ratio of a capacitance of the first parasitic capacitor to a capacitance of the second parasitic capacitor, because it would have been to obtain a certain ratio of a capacitance of the first parasitic capacitor to a capacitance of the second parasitic capacitor to achieve enhance controlling the switch threshold voltage.
Reclaim 2, Ma fails to specify that the ratio of the capacitance of the first parasitic capacitor to the capacitance of the second parasitic capacitor is between 2.3 to 3.5.
However, notwithstanding, one of ordinary skill in the art would have been led to the recited dimensions through routine experimentation and optimization.
Before effective filing date of the invention it would have been obvious to a person of ordinary skill in the art to use a certain ratio of a capacitance of the first parasitic capacitor to a capacitance of the second parasitic capacitor, because it would have been to obtain a certain ratio of a capacitance of the first parasitic capacitor to a capacitance of the second parasitic capacitor to achieve enhance controlling the switch threshold voltage.
Reclaim 3, Ma discloses that a the first node connecting line crosses over the respective second gate line; in a region where an orthographic projection of the first node connecting line on the base substrate overlaps with an orthographic projection of the respective second gate line on the base substrate, the array substrate is absent of any other conductive component whose orthographic projection on the base substrate overlaps with the orthographic projection of the first node connecting line on the base substrate; and the first node connecting line is in a layer that is spaced apart from the respective second gate line by at least two different insulating layers and a semiconductor material layer (Fig. 2).
Reclaim 13, Ma discloses that a plurality of first voltage supply lines and a plurality of light emitting control signal lines; wherein a respective pixel driving circuit of the plurality of pixel driving circuits comprises a first light emitting control transistor, and a voltage connecting pad; wherein the voltage connecting pad comprises a main portion and an extension portion extending away from the main portion; the main portion connects a respective first voltage supply line of the plurality of first voltage supply lines with a second capacitor electrode of the storage capacitor; the extension portion connects the main portion with a first electrode of the first light emitting control transistor; and the extension portion crosses over a respective light emitting control signal line of the plurality of light emitting control signal lines (Fig. 2).
Reclaim 20, Ma discloses that an array substrate, comprising a plurality of first gate lines, a plurality of second gate lines, and a plurality of pixel driving circuits;
wherein a respective pixel driving circuit of the plurality of pixel driving circuits comprises a driving transistor T1 or T2, a data write transistor DTFT, a compensating transistor T3, a storage capacitor, a first node connecting line connecting a gate electrode of the driving transistor with a first electrode of the compensating transistor T3;
a respective first gate line A-DTFT of the plurality of first gate lines configured to provide a gate scanning signal Ref2 to the data write transistor DTFT;
a respective second gate line of the plurality of second gate lines configured to provide a gate scanning signal Ref2 to the compensating transistor T3;
wherein the array substrate comprises a first semiconductor material layer and a second semiconductor material layer on a side of the first semiconductor material layer away from a base substrate (Stack of transistors includes) ;
the first semiconductor material layer comprises at least active layers of the driving transistor and the data write transistor (a channel of the driving transistor T1 or T2 and a channel of DTFT);
the second semiconductor material layer (a channel of the T3 transistor) comprises at least an active layer of the compensating transistor;
a first parasitic capacitor C1 is formed between the second semiconductor material layer and the respective first gate line;
a second parasitic capacitor C1 is formed between the first node connecting line and the respective second gate line;
the respective first gate line comprises a respective first gate line first branch in a first gate metal layer and a respective first gate line second branch in a first signal line layer on a side of the first gate metal layer away from the base substrate; the respective first gate line second branch is connected to the respective first gate line first branch through one or more vias; the first parasitic capacitor is formed between the second semiconductor material layer and the respective first gate line first branch and between the second semiconductor material layer and the respective first gate line second branch (Fig. 2).
Ma fails to specify that capacitance of the first parasitic capacitor is greater than at least twice of a capacitance of the second parasitic capacitor.
However, notwithstanding, one of ordinary skill in the art would have been led to the recited dimensions through routine experimentation and optimization.
Before effective filing date of the invention it would have been obvious to a person of ordinary skill in the art to use a certain ratio of a capacitance of the first parasitic capacitor to a capacitance of the second parasitic capacitor, because it would have been to obtain a certain ratio of a capacitance of the first parasitic capacitor to a capacitance of the second parasitic capacitor to achieve enhance controlling the switch threshold voltage.
Reclaim 21, Ma discloses that a display apparatus, comprising the array substrate of claim 1, and one or more integrated circuits connected to the array substrate.
Allowable Subject Matter
Claims 4-12 & 14-18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SU C KIM whose telephone number is (571)272-5972. The examiner can normally be reached M-F 9:00 to 5:00.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dale Page can be reached at 571-270-7877. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SU C KIM/Primary Examiner, Art Unit 2899
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