Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed in parent Application No. DE10-2021-130017.7, filed on 11/17/2021.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the limitations and subject matter of Claims 11, 13 and 25 must be shown or the feature(s) canceled from the claim(s).
Claim 11 recites “A connection device… the connection device comprising: a first busbar for electrically connecting first poles of the high-voltage components; a second busbar for electrically connecting second poles of the high-voltage components; Y interference-suppression capacitors which are electrically connected to the first and second busbars and are able to be electrically connected to a reference potential…”, no Drawings or Figures depict, the “high-voltage components”, “first poles” of the “high-voltage components”, “second poles” of the “high-voltage components” or a “reference potential” of the connection device.
Claim 13 recites “wherein the respective planar areal portion and the respective electrically conductive planar areal part are mechanically connected to the respective insulation layer to form a one-piece assembly”, no Drawings or Figures depict, how the “respective planar areal portion” and “respective electrically conductive planar areal part” are “mechanically connected” to the “respective insulation layer” to form a one-piece assembly, the Drawings and Figures do not depict the means to “mechanically connect”, the “respective planar areal portion” and “respective electrically conductive planar areal part” to the “respective insulation layer”.
Claim 25 recites “wherein the intermediate circuit has a cooler forming the reference potential for the first and second Y interference-suppression capacitors”, no Drawings or Figures depict a “cooler” or “a cooler forming the reference potential for the first and second Y interference-suppression capacitors”.
No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections
Claims 11-26 are objected to because of the following informalities:
Claim 11 recites “a second electrically conductive planar areal part is arranged overlapped with the second areal portion to form a second Y interference-suppression capacitor” for consistency and clarity and to avoid antecedent issues, the limitations should be changed to read “a second electrically conductive planar areal part is arranged overlapped with the second planar areal portion to form a second Y interference-suppression capacitor”.
Claim 12 recites “which forms a dielectric of a respective Y interference-suppression capacitor, is arranged between a respective electrically conductive areal part and a respective areal portion” for consistency and clarity and to avoid antecedent issues, the limitations should be changed to read “which forms a dielectric of the respective Y interference-suppression capacitor, is arranged between the respective electrically conductive planar areal part and the respective planar areal portion”.
Claim 13 recites “wherein the respective areal portion and the respective areal part are mechanically connected” for consistency and clarity and to avoid antecedent issues, the limitations should be changed to read “wherein the respective planar areal portion and the respective electrically conductive planar areal part are mechanically connected”.
Claim 14-16 recites “wherein the overlapping areal portions of the first and second busbars” for consistency and clarity and to avoid antecedent issues, the limitations should be changed to read “wherein the overlapping first and second planar areal portions of the first and second busbars”.
Claim 17-19 recites “wherein a stack formed of the second areal part, the second areal portion, the first areal portion and the first areal part forms a carrier… the at least one intermediate-circuit capacitor being able to be electrically connected to the busbars” for consistency and clarity and to avoid antecedent issues, the limitations should be changed to read “wherein a stack formed of the second electrically conductive planar areal part, the second planar areal portion, the first planar areal portion and the first electrically conductive planar areal part forms a carrier… the at least one intermediate-circuit capacitor being able to be electrically connected to the first and second busbars”.
Claim 20 recites “wherein the first areal part and the first areal portion,… have passage openings for contacting the intermediate-circuit capacitor with the areal portions” for consistency and clarity and to avoid antecedent issues, the limitations should be changed to read “wherein the first electrically conductive planar areal part and the first planar areal portion,… have passage openings for contacting the at least one intermediate-circuit capacitor with the first and second planar areal portions”.
Claim 21-23 recites “the connection points being in the form of edge portions of the busbars arranged at two opposite edges of the areal portions and folded with respect to the areal portions” for consistency and clarity and to avoid antecedent issues, the limitations should be changed to read “the connection points being in the form of edge portions of the first and second busbars arranged at two opposite edges of the first and second planar areal portions and folded with respect to the first and second planar areal portions”.
Claim 24 recites “wherein the at least one intermediate-circuit capacitor is electrically connected to the busbars” for consistency and clarity and to avoid antecedent issues, the limitations should be changed to read “wherein the at least one intermediate-circuit capacitor is electrically connected to the first and second busbars”.
Claim 25 recites “a cooler forming the reference potential for the Y interference-suppression capacitors, wherein one of the areal parts” for consistency and clarity and to avoid antecedent issues, the limitations should be changed to read “a cooler forming the reference potential for the first and second Y interference-suppression capacitors, wherein one of the electrically conductive planar areal parts”.
Claim 12-26 are also objected to since they depend on Claim 11 and inherit the
deficiency therein.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 11-26 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by TAMURA et al. (CN-103368376-A - hereinafter, "Tamura").
With respect to Claim 11, Tamura teaches (in Figure 6-7, 9-10, 13 and as shown in annotated Figure 6 below)
A connection device (see annotated Figure 6 below) [for an intermediate circuit of a high-voltage on- board electrical system of a motor vehicle for electrically connecting high-voltage components of the high-voltage on-board electrical system] (Examiner notes “for an intermediate circuit of a high-voltage on- board electrical system of a motor vehicle for electrically connecting high-voltage components of the high-voltage on-board electrical system” is intended use, as stated in the MPEP, 2114 (ii): Apparatus claims cover what a device is, not what a device does. A claim containing a "recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus" if the prior art apparatus teaches all the structural limitations of the claim. Above statement within brackets “[ ]” does not differentiate the claimed apparatus from a prior art apparatus satisfying the claimed structural limitations.), the connection device (see Figure 6,9,13 and annotated Figure 6 below) comprising:
a first busbar (23) for electrically connecting first poles (terminals, in paragraph [0032], “In the module 21, output conductor 22 is connected on the regulation of every terminal, P conductor 23 and N conductor 24” of the provided translation, see annotated Figure 6 below) of the high-voltage components (21, in paragraph [0031], “under the condition that is modularly in units of circuit arms of the modular switching device module (hereinafter, referred to as "module")” and in paragraph [0032], “the module 21 is a module constituting the inverter circuit 14” of the provided translation);
a second busbar (24) for electrically connecting second poles (terminals, in paragraph [0032], “In the module 21, output conductor 22 is connected on the regulation of every terminal, P conductor 23 and N conductor 24” of the provided translation, see annotated Figure 6 below) of the high-voltage components (21);
Y interference-suppression capacitors (28a, 28b, in paragraph [0034], “the P-conductor 23 and the grounding conductor 25 of the extension setting part (first conductor part) between a Y-capacitor (P conductor Y capacitor) 28a is formed, the N-conductor 24 and the grounding conductor 25 is extended part between another Y-capacitor (N conductor Y capacitor) 28b is formed” of the provided translation) which are electrically connected to the first and second busbars (23,24) and are able to be electrically connected to a reference potential (25, in paragraph [0033], “the configuration the module carrying the ground conductor side 25 elongation; and further having as a property of an insulator dielectric 26a to form P conductor 23 near the module 21, and the ground conductor 25 on the opposite side, separated by the same insulator 26b, forms N conductor 21 near the module 24” of the provided translation) and which are designed to damp interference frequencies (in paragraph [0046] of the provided translation) emitted by at least one of the high-voltage components (21);
wherein the first busbar (23) has a first planar areal portion (see annotated Figure 6 below) and the second busbar (24) has a second planar areal portion (see annotated Figure 6 below) arranged overlapped with the first planar areal portion (see annotated Figure 6 below), and
the connection device (see Figure 6,9,13 and annotated Figure 6 below) has two electrically conductive planar areal parts (see annotated Figure 6 below) which are able to be connected to the reference potential (25), a first electrically conductive planar areal part (see annotated Figure 6 below) of the electrically conductive planar areal parts (see annotated Figure 6 below) is arranged overlapped with the first planar areal portion (see annotated Figure 6 below) to form a first Y interference-suppression capacitor (28a) and a second electrically conductive planar areal part (see annotated Figure 6 below) is arranged overlapped with the second planar areal portion (see annotated Figure 6 below) to form a second Y interference-suppression capacitor (28b).
PNG
media_image1.png
633
1023
media_image1.png
Greyscale
Figure I
with respect to Claim 12, Tamura further teaches (in Figure 6-7, 9-10, 13 and as shown in annotated Figure 6 above)
wherein an insulation layer (26a,26b), which forms a dielectric (in paragraph [0033], “a property of an insulator dielectric 26a to form P conductor 23 near the module 21, and the ground conductor 25 on the opposite side, separated by the same insulator 26b, forms N conductor 21 near the module 24” of the provided translation) of the respective Y interference-suppression capacitor (28a,28b), is arranged between the respective electrically conductive planar areal part (see annotated Figure 6 above) and the respective planar areal portion (see annotated Figure 6 above).
with respect to Claim 13, Tamura further teaches (in Figure 6-7, 9-10, 13 and as shown in annotated Figure 6 above)
wherein the respective planar areal portion (see annotated Figure 6 above) and the respective electrically conductive planar areal part (see annotated Figure 6 above) are mechanically connected (clamped, in paragraph [0042], “Specifically, as shown in FIG. 6, is formed, P-conductor 23 and the grounding conductor 25 of the extension setting part (first conductor part) opposite to the clamped insulator 26a, the N-conductor 24 and the grounding conductor 25 is extended part opposite to the middle holding insulator 26b, output conductor 22 extending setting part to the first I conductor part with different ground conductor 25 (first conductor unit (2) opposite to the clamped insulator 26c” of the provided translation) to the respective insulation layer (26a,26b) to form a one-piece assembly.
with respect to Claim 14-16, Tamura further teaches (in Figure 6-7, 9-10, 13 and as shown in annotated Figure 6 above)
wherein the two electrically conductive planar areal parts (see annotated Figure 6 above) are in a form of sub-areas (see annotated Figure 6 above) of an electrically conductive bent part (see annotated Figure 6 above) which are bent to form an envelope (see annotated Figure 6 above), wherein the overlapping first and second planar areal portions (see annotated Figure 6 above) of the first and second busbars (23,24) are arranged in the envelope between the sub-areas (see annotated Figure 6 above).
with respect to Claim 17-19, Tamura further teaches (in Figure 6-7, 9-10, 13 and as shown in annotated Figure 6 above)
wherein a stack (see annotated Figure 6 above) formed of the second electrically conductive planar areal part (see annotated Figure 6 above), the second planar areal portion (see annotated Figure 6 above), the first planar areal portion (see annotated Figure 6 above) and the first electrically conductive planar areal part (see annotated Figure 6 above) forms a carrier (see Figure 9, the at least one intermediate-circuit capacitor (28c) is seated in the stack (see annotated Figure 6 above) ) for at least one intermediate-circuit capacitor (28c) of the intermediate circuit (see Figure 7), the at least one intermediate-circuit capacitor (28c) being able to be electrically connected to the first and second busbars (23,24).
with respect to Claim 20, Tamura further teaches (in Figure 6-7, 9-10, 13 and as shown in annotated Figure 6 above)
wherein the first electrically conductive planar areal part (see annotated Figure 6 above) and the first planar areal portion (see annotated Figure 6 above), which face toward the at least one intermediate-circuit capacitor (28c), have passage openings (see annotated Figure 6 above, the gap between first busbar and the at least one intermediate-circuit capacitor (28c)) for contacting the at least one intermediate-circuit capacitor (28c) with the first and second planar areal portions (see annotated Figure 6 above).
with respect to Claim 21-23, Tamura further teaches (in Figure 6-7, 9-10, 13 and as shown in annotated Figure 6 above)
wherein the two busbars (23,24) have connection points (see annotated Figure 6 above) for the poles (terminals) of the high-voltage components (21), the connection points (see annotated Figure 6 above) being in the form of edge portions (see annotated Figure 6 above) of the first and second busbars (23,24) arranged at two opposite edges (see annotated Figure 6 above) of the first and second planar areal portions (see annotated Figure 6 above) and folded with respect to the first and second planar areal portions (see annotated Figure 6 above).
with respect to Claim 24, Tamura further teaches (in Figure 6-7, 9-10, 13 and as shown in annotated Figure 6 above)
An intermediate circuit (see Figure 7, 10) [for a high-voltage on-board electrical system of a motor vehicle] (Examiner notes “for a high-voltage on-board electrical system of a motor vehicle” is intended use, as stated in the MPEP, 2114 (ii): Apparatus claims cover what a device is, not what a device does. A claim containing a "recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus" if the prior art apparatus teaches all the structural limitations of the claim. Above statement within brackets “[ ]” does not differentiate the claimed apparatus from a prior art apparatus satisfying the claimed structural limitations.),
having at least one intermediate-circuit capacitor (28c) and
at least one connection device (see annotated Figure 6 above) according to claim11,
wherein the at least one intermediate-circuit capacitor (28c) is electrically connected to the first and second busbars (23,24).
with respect to Claim 25, Tamura further teaches (in Figure 6-7, 9-10, 13 and as shown in annotated Figure 6 above)
wherein the intermediate circuit (see Figure 7, 10) has a cooler (50, see Figure 13, ) forming the reference potential (25) for the first and second Y interference-suppression capacitors (28a,28b), wherein one of the electrically conductive planar areal parts (see annotated Figure 6 above) is arranged lying on the cooler (50) and electrically connected to the reference potential (25).
with respect to Claim 26, Tamura further teaches (in Figure 6-7, 9-10, 13 and as shown in annotated Figure 6 above)
A high-voltage on-board electrical system () [for a motor vehicle] (Examiner notes “for a motor vehicle” is intended use, as stated in the MPEP, 2114 (ii): Apparatus claims cover what a device is, not what a device does. A claim containing a "recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus" if the prior art apparatus teaches all the structural limitations of the claim. Above statement within brackets “[ ]” does not differentiate the claimed apparatus from a prior art apparatus satisfying the claimed structural limitations.) having at least two high-voltage components (switching elements, an other (21), in paragraph [0031], “The switching elements UP1, VP1, WP1, UN1, VN1, WNI, modular, carried on the semiconductor substrate. a plurality of unit for modular, it not only has all the switching elements is modularly, also in units of circuit for modular arm… In addition, under the condition that is modularly in units of circuit arms of the modular switching device module (hereinafter, referred to as "module" ” of the provided translation) and
an intermediate circuit (see Figure 7, 10) according to claim 24,
wherein the high-voltage components (21) are electrically connected to the intermediate circuit (see Figure 7, 10).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 2024/0213886 to NISHIZAWA, which teaches a power conversion device includes: a power conversion circuit that converts DC power into AC power; a positive electrode bus bar and a negative electrode bus bar connected to the power conversion circuit; a capacitor connected to at least one of the positive electrode bus bar and the negative electrode bus bar; a base plate made of metal on which the capacitor is placed. In addition, as the frequency of the switching elements in the power conversion device is increased, the noise removing capacitor for suppressing noise due to the high frequency needs to be arranged near the DC bus bar.
US 2011/0037536 to Kanno et al., which teaches a capacitance element includes a first electrode, a second electrode, a third electrode, a fourth electrode, a first dielectric portion, a second dielectric portion, and a third dielectric portion. a response of the reception signal at a resonance frequency before the capacitance is changed is reduced as compared to the state before the capacitance is changed, thereby suppressing the level of the reception signal. As a result, it is possible to prevent the excessive current signals from being supplied to the control circuit, which can prevent the breakdown of the control circuit.
US 2009/0059467 to Grimm et al., which teaches a power electronics module includes a capacitor having a trough-shaped housing and at least one capacitor winding. An electronic unit includes a base on which the capacitor is mounted. A cooling plate in thermal contact with a cooling surface of the capacitor is formed by a bus bar. The cooling plate is on the base of the electronic unit.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Steven Ngo whose telephone number is (571)272-4295. The examiner can normally be reached Monday - Friday 7:30AM - 4:00PM EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jayprakash Gandhi can be reached at (571) 272-3740. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/S.N./Examiner , Art Unit 2835
/Jayprakash N Gandhi/Supervisory Patent Examiner, Art Unit 2835
Prosecution Insights