Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed in parent Application No. DE10-2021-130017.7, filed on 11/17/2021.
Drawings
The objections to the drawings are withdrawn in view of the amendments to Claims 11, 13 and 25.
Claim Objections
The objections to the Claims 11-14, 17-19, 21-25 are withdrawn in view of the amendments to the Claims 11-14, 17-19, 21-25.
Claims 11-24, 26 objected to because of the following informalities:
Claim 11 recites “a second electrically conductive planar areal part is arranged overlapped with the second planar areal portion to form a second Y interference-suppression capacitor” for consistency similar to “a first electrically conductive planar areal part”, the limitations should be changed to read “a second electrically conductive planar areal part of the two electrically conductive planar areal parts is arranged overlapped with the second planar areal portion to form a second Y interference-suppression capacitor”.
Claim 15-16 recites “wherein the overlapping areal portions of the first and second busbars” for consistency and clarity and to avoid antecedent issues, the limitations should be changed to read “wherein the overlapping first and second planar areal portions of the first and second busbars”.
Claim 20 recites “wherein the first areal part and the first areal portion,… have passage openings for contacting the intermediate-circuit capacitor with the areal portions” for consistency and clarity and to avoid antecedent issues, the limitations should be changed to read “wherein the first electrically conductive planar areal part and the first planar areal portion,… have passage openings for contacting the at least one intermediate-circuit capacitor with the first and second planar areal portions”.
Claim 12-24, 26 are also objected to since they depend on Claim ## and inherit the deficiency therein.
Claim 20 are also objected to since they depend on Claim 15 and inherit the
deficiency therein.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 11-24, 26 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by TAMURA et al. (CN-103368376-A - hereinafter, "Tamura").
With respect to Claim 11, Tamura teaches (in Figure 6-7, 9-10, 13 and as shown in annotated Figure 6 below)
A connection device (see annotated Figure 6 below) [for an intermediate circuit of a high-voltage on- board electrical system of a motor vehicle] (Examiner notes “for an intermediate circuit of a high-voltage on- board electrical system of a motor vehicle” is intended use, as stated in the MPEP, 2114 (ii): Apparatus claims cover what a device is, not what a device does. A claim containing a "recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus" if the prior art apparatus teaches all the structural limitations of the claim. Above statement within brackets “[ ]” does not differentiate the claimed apparatus from a prior art apparatus satisfying the claimed structural limitations.), the connection device (see Figure 6,9,13 and annotated Figure 6 below) comprising:
a first busbar (23);
a second busbar (24);
Y interference-suppression capacitors (28a, 28b, in paragraph [0034], “the P-conductor 23 and the grounding conductor 25 of the extension setting part (first conductor part) between a Y-capacitor (P conductor Y capacitor) 28a is formed, the N-conductor 24 and the grounding conductor 25 is extended part between another Y-capacitor (N conductor Y capacitor) 28b is formed” of the provided translation) which are electrically connected to the first and second busbars (23,24, in paragraph [0033], “the configuration the module carrying the ground conductor side 25 elongation; and further having as a property of an insulator dielectric 26a to form P conductor 23 near the module 21, and the ground conductor 25 on the opposite side, separated by the same insulator 26b, forms N conductor 21 near the module 24” of the provided translation) and which are designed to damp interference frequencies (in paragraph [0046] of the provided translation);
wherein the first busbar (23) has a first planar areal portion (see annotated Figure 6 below) and the second busbar (24) has a second planar areal portion (see annotated Figure 6 below) arranged overlapped with the first planar areal portion (see annotated Figure 6 below), and
the connection device (see Figure 6,9,13 and annotated Figure 6 below) has two electrically conductive planar areal parts (see annotated Figure 6 below) that are separate from the first and second planar areal portions (see annotated Figure 6 below),
a first electrically conductive planar areal part (see annotated Figure 6 below) of the two electrically conductive planar areal parts (see annotated Figure 6 below) is arranged overlapped with the first planar areal portion (see annotated Figure 6 below) to form a first Y interference-suppression capacitor (28a) and
a second electrically conductive planar areal part (see annotated Figure 6 below) of the two electrically conductive planar areal parts (see annotated Figure 6 below) is arranged overlapped with the second planar areal portion (see annotated Figure 6 below) to form a second Y interference-suppression capacitor (28b).
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with respect to Claim 12, Tamura further teaches (in Figure 6-7, 9-10, 13 and as shown in annotated Figure 6 above)
wherein an insulation layer (26a,26b), which forms a dielectric (in paragraph [0033], “a property of an insulator dielectric 26a to form P conductor 23 near the module 21, and the ground conductor 25 on the opposite side, separated by the same insulator 26b, forms N conductor 21 near the module 24” of the provided translation) of the first and second Y interference-suppression capacitor (28a,28b), is arranged between the first and second electrically conductive planar areal part (see annotated Figure 6 above) and the first and second planar areal portions respectively (see annotated Figure 6 above).
with respect to Claim 13, Tamura further teaches (in Figure 6-7, 9-10, 13 and as shown in annotated Figure 6 above)
wherein the first planar areal portion (see annotated Figure 6 above) and the first electrically conductive planar areal part (see annotated Figure 6 above) form a first one-piece assembly (23+25+26a are clamped to form one-piece, (first conductor part), in paragraph [0041], “Specifically, as shown in FIG. 6, is formed, P-conductor 23 and the grounding conductor 25 of the extension setting part (first conductor part) opposite to the clamped insulator 26a, the N-conductor 24 and the grounding conductor 25 is extended part opposite to the middle holding insulator 26b” of the provided translation), and the second planar areal portion (see annotated Figure 6 above) and the second electrically conductive planar areal part (see annotated Figure 6 above) form a second one-piece assembly (24+25+26b are clamped to form another one-piece, in paragraph [0041], “Specifically, as shown in FIG. 6, is formed, P-conductor 23 and the grounding conductor 25 of the extension setting part (first conductor part) opposite to the clamped insulator 26a, the N-conductor 24 and the grounding conductor 25 is extended part opposite to the middle holding insulator 26b” of the provided translation).
with respect to Claim 14-16, Tamura further teaches (in Figure 6-7, 9-10, 13 and as shown in annotated Figure 6 above)
wherein the two electrically conductive planar areal parts (see annotated Figure 6 above) are in a form of sub-areas (see annotated Figure 6 above) of an electrically conductive bent part (see annotated Figure 6 above) which are bent to form an envelope (see annotated Figure 6 above), wherein the overlapping first and second planar areal portions (see annotated Figure 6 above) of the first and second busbars (23,24) are arranged in the envelope between the sub-areas (see annotated Figure 6 above).
with respect to Claim 17-19, Tamura further teaches (in Figure 6-7, 9-10, 13 and as shown in annotated Figure 6 above)
wherein a stack (see annotated Figure 6 above) formed of the second electrically conductive planar areal part (see annotated Figure 6 above), the second planar areal portion (see annotated Figure 6 above), the first planar areal portion (see annotated Figure 6 above) and the first electrically conductive planar areal part (see annotated Figure 6 above) forms a carrier (see Figure 9, the at least one intermediate-circuit capacitor (28c) is seated in the stack (see annotated Figure 6 above) ) for at least one intermediate-circuit capacitor (28c) of the intermediate circuit (see Figure 7), the at least one intermediate-circuit capacitor (28c) being able to be electrically connected to the first and second busbars (23,24).
with respect to Claim 20, Tamura further teaches (in Figure 6-7, 9-10, 13 and as shown in annotated Figure 6 above)
wherein the first electrically conductive planar areal part (see annotated Figure 6 above) and the first planar areal portion (see annotated Figure 6 above), which face toward the at least one intermediate-circuit capacitor (28c), have passage openings (see annotated Figure 6 above, the gap between first busbar and the at least one intermediate-circuit capacitor (28c)) for contacting the at least one intermediate-circuit capacitor (28c) with the first and second planar areal portions (see annotated Figure 6 above).
with respect to Claim 21-23, Tamura further teaches (in Figure 6-7, 9-10, 13 and as shown in annotated Figure 6 above)
wherein the two busbars (23,24) have connection points (see annotated Figure 6 above) in the form of edge portions (see annotated Figure 6 above) of the first and second busbars (23,24) arranged at two opposite edges (see annotated Figure 6 above) of the first and second planar areal portions (see annotated Figure 6 above) and folded with respect to the first and second planar areal portions (see annotated Figure 6 above).
with respect to Claim 24, Tamura further teaches (in Figure 6-7, 9-10, 13 and as shown in annotated Figure 6 above)
An intermediate circuit (see Figure 7, 10) [for a high-voltage on-board electrical system of a motor vehicle] (Examiner notes “for a high-voltage on-board electrical system of a motor vehicle” is intended use, as stated in the MPEP, 2114 (ii): Apparatus claims cover what a device is, not what a device does. A claim containing a "recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus" if the prior art apparatus teaches all the structural limitations of the claim. Above statement within brackets “[ ]” does not differentiate the claimed apparatus from a prior art apparatus satisfying the claimed structural limitations.),
having at least one intermediate-circuit capacitor (28c) and
at least one connection device (see annotated Figure 6 above) according to claim11,
wherein the at least one intermediate-circuit capacitor (28c) is electrically connected to the first and second busbars (23,24).
with respect to Claim 26, Tamura further teaches (in Figure 6-7, 9-10, 13 and as shown in annotated Figure 6 above)
A high-voltage on-board electrical system () [for a motor vehicle] (Examiner notes “for a motor vehicle” is intended use, as stated in the MPEP, 2114 (ii): Apparatus claims cover what a device is, not what a device does. A claim containing a "recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus" if the prior art apparatus teaches all the structural limitations of the claim. Above statement within brackets “[ ]” does not differentiate the claimed apparatus from a prior art apparatus satisfying the claimed structural limitations.) having
an intermediate circuit (see Figure 7, 10) according to claim 24.
Response to Arguments
Applicant’s arguments filed on 07/06/2026 have been fully considered, the Examiner notes that Applicant’s arguments are directed to the claims as amended, and the rejection has been modified to meet the limitations of the amended claims (See rejection above).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/S.N./Examiner, Art Unit 2841
/Jayprakash N Gandhi/Supervisory Patent Examiner, Art Unit 2841
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