Prosecution Insights
Last updated: July 17, 2026
Application No. 18/689,669

SEMICONDUCTOR APPARATUS AND METHOD FOR MANUFACTURING SEMICONDUCTOR APPARATUS

Non-Final OA §103
Filed
Mar 06, 2024
Priority
Sep 08, 2021 — JP 2021-146089 +2 more
Examiner
ISAAC, STANETTA D
Art Unit
2898
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Toyobo Co., Ltd.
OA Round
1 (Non-Final)
86%
Grant Probability
Favorable
1-2
OA Rounds
1m
Est. Remaining
48%
With Interview

Examiner Intelligence

Grants 86% — above average
86%
Career Allowance Rate
824 granted / 963 resolved
+17.6% vs TC avg
Minimal -37% lift
Without
With
+-37.1%
Interview Lift
resolved cases with interview
Typical timeline
2y 5m
Avg Prosecution
47 currently pending
Career history
1022
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
62.7%
+22.7% vs TC avg
§102
35.6%
-4.4% vs TC avg
§112
1.4%
-38.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 963 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . This office action is in response to the application filed on 03/06/24. Claims 1-7 are pending. Priority Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55. Information Disclosure Statement The information disclosure statements (IDS) were submitted on 3/06/24, 4/04/24, 2/04/25, 6/25/25, and 3/23/26. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. Specification The specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claim(s) 1-7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sadanobu et al. (EPO 1 275681 B1, hereinafter to referred to as “Sadanobu”) in view of Takeguchi et al. (US PGPub 2007/0272927, hereinafter referred to as “Takeguchi”). Sadanobu discloses the semiconductor apparatus and method as claimed. See corresponding text, where Sadanobu teaches, in claim 1, a semiconductor apparatus comprising: a base film; wherein the base film is a polyimide film obtained by poly condensation of an aromatic diamine and an aromatic tetracarboxylic anhydride and has a tensile modulus of 7 GPa or more in a machine direction ([0017-0028], [0060]). Sadanobu fails to teach, in claim 1, a semiconductor film formed on the base film; the semiconductor film is a polycrystalline film formed from crystal grains having an average grain size of 1 μm or more. Takeguchi teaches, in claim 1, a semiconductor film formed on a base film and the device is formed on a wiring board that is a flexible printed circuit (FPC) ([0039] [0032], [0053]). In addition, Takeguchi provides the advantages of having a active matrix type display device having stable characteristics ([0016]). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to incorporate, a semiconductor film formed on the base film; the semiconductor film is a polycrystalline film formed from crystal grains having an average grain size of 1 μm or more, in the device and method of Sadanobu, according to the teachings of Takeguchi, with the motivation of having stable characteristics of the semiconductor device. Sadanobu in view of Takeguchi teaches, in claim 2, wherein the base film has a coefficient of linear thermal expansion of 5 ppm/° C. or less ([0017-0028], [0060], Sadanobu). Sadanobu teaches, in claim 3, a method for manufacturing a semiconductor apparatus including a base film and a semiconductor film formed on the base film, the base film being a polyimide film obtained by poly condensation of an aromatic diamine and an aromatic tetracarboxylic anhydride and having a tensile modulus of 7 GPa or more in a machine direction. Sadanobu fails to teach, in claim 3, semiconductor film formed on the base film; the semiconductor film is a polycrystalline film formed from crystal grains having an average grain size of 1 μm or more ; the method comprising: a first step of forming an amorphous semiconductor film on one surface of the base film while heating the base film; and a second step of heating the semiconductor film to promote solid phase growth of the semiconductor film, wherein a heating temperature in the first step is adjusted to be 50% or more and less than 100% of a temperature at which a crystal nucleus is generated in the semiconductor film Takeguchi teaches, in claim 1, a semiconductor film formed on a base film and the device is formed on a wiring board that is a flexible printed circuit (FPC) ([0039] [0032], [0053]), and the semiconductor film being a polycrystalline film formed from crystal grains having an average grain size of 1 μm or more, the method comprising: a first step of forming an amorphous semiconductor film on one surface of the base film while heating the base film; and a second step of heating the semiconductor film to promote solid phase growth of the semiconductor film, wherein a heating temperature in the first step is adjusted to be 50% or more and less than 100% of a temperature at which a crystal nucleus is generated in the semiconductor film. In addition, Takeguchi provides the advantages of having a active matrix type display device having stable characteristics ([0016]) Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to incorporate, semiconductor film formed on the base film; the semiconductor film is a polycrystalline film formed from crystal grains having an average grain size of 1 μm or more ; the method comprising: a first step of forming an amorphous semiconductor film on one surface of the base film while heating the base film; and a second step of heating the semiconductor film to promote solid phase growth of the semiconductor film, wherein a heating temperature in the first step is adjusted to be 50% or more and less than 100% of a temperature at which a crystal nucleus is generated in the semiconductor film, in the device and method of Sadanobu, according to the teachings of Takeguchi, with the motivation of having stable characteristics of the semiconductor device. Sadanobu in view of Takeguchi teaches, in claim 4, wherein a heating temperature in the first step is adjusted so that a density of grains constituting the semiconductor film is 98% or more and less than 102% of a density of grains in a crystal of the same material ([0017-0028], [0060], Sadanobu). Sadanobu in view of Takeguchi teaches, in claim 5, wherein a heating temperature in the first step is set to 100° C. or more and 150° C. or less ([0017-0028], [0060], Sadanobu). Sadanobu in view of Takeguchi teaches, in claim 6, wherein a heating temperature in the second step is set to 350° C. or more and 800° C. or less ([0017-0028], [0060], Sadanobu). Sadanobu in view of Takeguchi teaches, in claim 7, wherein the base film has a coefficient of linear thermal expansion of 5 ppm/° C. or less ([0017-0028], [0060], Sadanobu). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to STANETTA D ISAAC whose telephone number is (571)272-1671. The examiner can normally be reached M-F 10-6. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Leonard Chang can be reached at 571-270-3691. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /STANETTA D ISAAC/Examiner, Art Unit 2898 June 13, 2026
Read full office action

Prosecution Timeline

Mar 06, 2024
Application Filed
Jun 17, 2026
Non-Final Rejection mailed — §103 (current)

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
86%
Grant Probability
48%
With Interview (-37.1%)
2y 5m (~1m remaining)
Median Time to Grant
Low
PTA Risk
Based on 963 resolved cases by this examiner. Grant probability derived from career allowance rate.

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