DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This office action is in response to the amendment filed on 6/24/26. Claims 18-34 are pending.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 18-34 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Bouvier et al. (US PGPub 2016/0218240, hereinafter referred to as “Bouvier”, IDS reference).
Bouvier discloses the semiconductor device and method as claimed. See figures 1-26 and corresponding text, where Bouvier teaches, in claim 18, an optoelectronic component comprising: (figures 2a-2f; [0060-0120])
at least one semiconductor body (10) including a first semiconductor region (30) (left side), a second semiconductor region (30) (right side) and an active region (34) therebetween, wherein the active region is configured to generate electromagnetic radiation (figure 2A; [0068], [0085-0087]);
a cover element (34) laterally surrounding the at least one semiconductor body and having at least one patterned side surface facing away from the at least one semiconductor body, wherein the cover element contains an index-matched dielectric material (figures 2a-2f; [0060-0120]); and
a reflection element (38), which at least partly covers the at least one patterned side surface, wherein the active region (34) is at least partly laterally surrounded by the first semiconductor region (figures 2a-2f; [0060-0120], [0089]).
Bouvier teaches, in claim 19, wherein the reflection element laterally surrounds the at least one semiconductor body (figures 2a-2f; [0060-0120]).
Bouvier teaches, in claim 20, wherein the optoelectronic component comprises at least two semiconductor bodies, whose first semiconductor regions form one continuous region and/or whose second semiconductor regions form one continuous region (figures 2a-2f; [0060-0120]).
Bouvier teaches, in claim 21, further comprising:
] a first electrical contact structure comprising a first contact layer (54); and
a second electrical contact structure comprising a second contact layer (52), wherein each of the first and second contact layers is in electrical contact with the at least one semiconductor body (figures 2a-2f; [0060-0120]).
Bouvier teaches, in claim 22, wherein the first electrical contact structure comprises a vertical contact portion (54) covering the reflection element at the at least one patterned side surface (figures 2a-2f; [0060-0120]).
Bouvier teaches, in claim 23, further comprising an insulation layer arranged between the vertical contact portion and the second contact layer (figures 2a-2f; [0060-0120]).
Bouvier teaches, in claim 24, wherein the insulation layer (48) originates from a mask layer and comprises at least one opening, in which one semiconductor body is partly arranged (figures 2a-2f; [0060-0120]).
Bouvier teaches, in claim 25, further comprising a reinforcement element, on which the at least one semiconductor body is arranged, wherein a lateral contact portion of the first electrical contact structure is arranged between the at least one semiconductor body and the reinforcement element (figures 2a-2f; [0060-0120]).
Bouvier teaches, in claim 26, wherein the cover elements of at least a part of the optoelectronic components are formed from one common cover layer (figures 2a-2f; [0060-0120]).
Bouvier teaches, in claim 27, wherein the reflection elements of at least a part of the optoelectronic components are formed from one common reflection layer (figures 2a-2f; [0060-0120]).
Bouvier teaches, in claim 28, wherein the common cover layer comprises at least one opening, in which the reflection layer is arranged (figures 2a-2f; [0060-0120]).
Bouvier teaches, in claim 29, wherein the first electrical contact structures of at least a part of the optoelectronic components form a common first electrical contact structure of the component unit, and/or wherein the second electrical contact structures of the same or another part of the optoelectronic components form a common second electrical contact structure of the component unit (figures 2a-2f; [0060-0120]).
Bouvier teaches, in claim 30, wherein the at least one patterned side surface is tilted and includes an angle with a main extension plane, wherein the angle is greater than 900 and smaller than 1800 and wherein the angle is optimized to improve radiation mission and directionality (figures 2a-2f; [0060-0120]).
Bouvier teaches, in claim 31, the method comprising: (figure 2A-2D; [0059-0113])
providing a growth substrate (10) having a mask layer with openings arranged thereon;
forming, in the openings, a plurality of semiconductor bodies (DEL);
forming a cover layer (34) on the growth substrate (10) such that the cover layer laterally surrounds at least a part of the semiconductor bodies (DEL);
patterning the cover layer (34) to produce at least one cover element containing the index-matched dielectric material and having the at least one patterned side surface, wherein patterning includes producing at least one opening in the cover layer, which is at least partly delimited by the at least one patterned side surface; and
forming a reflection layer (38) for producing reflection elements in the at least one opening of the cover layer such that it covers at least partly the at least one patterned side surface, wherein each active region (34) is produced such that it is at least partly laterally surrounded by the respective first semiconductor region (figure 2A; [0060-0090]).
Bouvier teaches, in claim 32, further comprising arranging a reinforcement layer on a side of the semiconductor bodies facing away from the growth substrate (figure 2A-2D; [0059-0113])
.
Bouvier teaches, in claim 33, further comprising detaching the growth substrate (figure 1; [0050]).
Bouvier teaches, in claim 34, wherein a semiconductor layer is arranged between the growth substrate and the mask layer, and wherein at least parts of the semiconductor layer form second contact layers of the optoelectronic components (figure 2A; [0060]).
Response to Arguments
Applicant’s arguments with respect to claim(s) 18-34 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Applicant’s amendment has necessitated new grounds of rejection.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to STANETTA D ISAAC whose telephone number is (571)272-1671. The examiner can normally be reached M-F 10-6.
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/STANETTA D ISAAC/Examiner, Art Unit 2898 September 5, 2026
/Leonard Chang/Supervisory Patent Examiner, Art Unit 2898
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