Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yu et al., US 2015/0325497.
Regarding claim 1, Yu discloses (figs. 21-30 and related text) a semiconductor device (fig. 30), comprising: a substrate (2106) on which a rewiring layer (2114) is formed; an etching stopper layer (2802 is formed from 902, silicon nitride [0027], hence can serve as an etch stop layer) formed on a bonding surface of the rewiring layer (2114); a die (2102, [0049]) bonded to a partial region of the bonding surface (fig. 30) via the etching stopper layer (2802); and an isolation film (2116) covering the die (2102) and the etching stopper layer (2802, fig. 30), wherein the etching stopper layer is a layer of silicon carbide ([0021] and [0027]).
Regarding claim 2, Yu discloses a substrate-side via (fig. 30) penetrating the isolation film (2116) and the etching stopper layer (2802) and having one end connected to a wiring in the rewiring layer (2114); and a die-side via penetrating the isolation film (2116), the die (2102), and the etching stopper layer (2802) and having one end connected to the wiring (2110) in the rewiring layer.
Regarding claim 3, Yu discloses the die-side via is formed at a location that does not correspond to an end of the die (left side of fig. 30).
Regarding claim 4, Yu discloses the die-side via is formed at an end of the die (middle of fig. 30).
Regarding claim 5, Yu discloses an etching rate when etching the etching stopper layer with a predetermined etching gas is lower than an etching rate when etching the isolation film with the etching gas (since Yu discloses the isolation film is one of silicon oxide [0018], etching the etching stopper of silicon nitride (902), the etching stopper layer with a predetermined etching gas is lower than an etching rate when etching the isolation film).
Regarding claim 6, Yu discloses the isolation film is a silicon oxide film [0018].
Regarding claim 7, Yu discloses semiconductor device (fig. 30), comprising: a substrate (2106) on which a rewiring layer (2108) is formed; a die (2102) bonded to a partial region of a bonding surface of the rewiring layer (2108); a first isolation film (2116) covering the die (2102) and the rewiring layer (2108); a second isolation film (the isolation layer inside 2114); and an etching stopper layer (2802) formed between the first isolation film (2116) and the second isolation film (the isolation layer inside of 2114) and having a step near an end of the die (2802 have a step shape near the die), wherein the etching stopper layer is a layer of silicon carbide ([0021] and [0027]).
Regarding claim 8, Yu discloses a substrate-side via penetrating the first isolation film (2116) and the second isolation film (inside 2114) and the etching stopper layer (between 2802) and having one end connected to a wiring (2110) in the rewiring layer (2108); and a die-side via penetrating the first isolation film (left side of fig. 30) and the second isolation film (inside 2114), the etching stopper layer (between 2802), and the die (2102) and having one end connected to the wiring in the rewiring layer (2108).
Regarding claim 9, Yu discloses the die-side via is formed at a location that does not correspond to an end of the die (right side of fig. 30).
Regarding claim 10, Yu discloses the die-side via is formed at an end of the die (left hand side of fig. 30).
Regarding claim 11, Yu discloses (fig. 30 and related text) a method for manufacturing a semiconductor device (fig. 30), comprising: an etching stopper layer (from 902 to 2802) forming procedure for forming an etching stopper layer (902 can be silicon nitride) on a bonding surface of a rewiring layer (2108) formed on a substrate (2106); a bonding procedure for bonding a die (2102) to a partial region of the bonding surface via the etching stopper layer (2802); and an isolation film (2116) forming procedure for forming an isolation film covering the die (2102) and the etching stopper layer (2802), wherein the etching stopper layer is a layer of silicon carbide ([0021] and [0027]).
Regarding claim 12, Yu discloses (fig. 30 and related process step including related text) a method for manufacturing a semiconductor device (fig. 30), comprising: a bonding procedure for bonding a die (2102) to a partial region of a bonding surface of a rewiring layer (2108) formed on a substrate (2106); a first isolation film forming (forming 2114 includes forming an insulation layer) procedure for forming a first isolation film (2114) covering the die (2102 from the bottom) and the rewiring layer (2108 from the bottom); an etching stopper layer forming procedure (902 to 2802) for forming an etching stopper layer (902 is made of silicon nitride hence can serve as an etch stop) having a step near an end of the die (fig. 30); and a second isolation film (isolation layer in 2116) forming procedure for forming a second isolation film covering the etching stopper layer (2802), wherein the etching stopper layer is a layer of silicon carbide ([0021] and [0027]).
Regarding claim 13, Yu discloses a penetrating procedure for penetrating a substrate-side via through the first isolation film (2116) and the second isolation film (inside 2114) and the etching stopper layer (between 2802) and having one end connected to a wiring in the rewiring layer (2108); and a penetrating procedure for penetrating a die-side via through the first isolation film (left side of fig. 30) and the second isolation film (inside 2114), the etching stopper layer (between 2802), and the die (2102) and having one end connected to the wiring in the rewiring layer (2108).
Regarding claim 14, Yu discloses the die-side via at a location that does not correspond to an end of the die (right side of fig. 30).
Regarding claim 15, Yu discloses forming the die-side via at an end of the die (left hand side of fig. 30).
Regarding claim 16, Yu discloses a penetrating procedure for penetrating a substrate-side via through the first isolation film (2116) and the second isolation film (inside 2114) and the etching stopper layer (between 2802) and having one end connected to a wiring in the rewiring layer (2108); and a penetrating procedure for penetrating a die-side via through the first isolation film (left side of fig. 30) and the second isolation film (inside 2114), the etching stopper layer (between 2802), and the die (2102) and having one end connected to the wiring in the rewiring layer (2108).
Regarding claim 17, Yu discloses the die-side via at a location that does not correspond to an end of the die (right side of fig. 30).
Regarding claim 18, Yu discloses forming the die-side via at an end of the die (left hand side of fig. 30).
Regarding claim 19, Yu discloses an etching rate when etching the etching stopper layer with a predetermined etching gas is lower than an etching rate when etching the isolation film with the etching gas (since Yu discloses the isolation film is one of silicon oxide [0018], etching the etching stopper of silicon nitride (902), the etching stopper layer with a predetermined etching gas is lower than an etching rate when etching the isolation film).
Regarding claim 20, Yu discloses the isolation film is a silicon oxide film [0018].
Response to Arguments
Applicant's arguments filed 08/18/2026 have been fully considered but they are not persuasive. Applicant argues that Yu fails to disclose the etching stopper layer is a layer of silicon carbide or silicon carbonitride. This argument is not persuasive as stated above in the rejection above Yu clearly discloses that silicon carbide can be used as the layers for making 902. Therefore, Yu anticipates the claimed layer.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SAMUEL A GEBREMARIAM whose telephone number is (571)272-1653. The examiner can normally be reached 8:30-4PM.
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/SAMUEL A GEBREMARIAM/Primary Examiner, Art Unit 2811
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