Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 29-34 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. The limitation “substrate” as recited in lines 2, 5 and 13 is unclear whether the limitation is referring back to the metallic substrate or not. Furthermore, it is not clear what the structural relationship is between the claimed substrate and first and second metallic region.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 18-20, 22-25, 27, and 29-31 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lim et al., US 20200212276.
Regarding claim 18, Lim discloses (figs. 1-2 and related text) an optoelectronic device (100) comprising: a lead frame (111, 112, 153) with a first metallic region (the second portion 111 from left to right) and at least one second metallic region (153 below 120A) spaced therefrom (fig. 2), wherein the first metallic region (111) and the at least one second metallic region (153) form a first cavity (region where R1, 113, and TH1-TH2 are formed) on a first side of the lead frame (bottom side of 100); at least one electrical component (TH1/TH2 serves as a conductive path for electrical signals between layers, hence electrical component), which is arranged in the first cavity and molded with a mold compound (113/135), and which electrically connects the first metallic region and the at least one second metallic region to one another (through 121/122); and at least one optoelectronic component (120A/120B), which electrically connects the first metallic region (111) and the second metallic region (153) on a second side of the lead frame facing away from the first cavity (fig. 2); or at least one optoelectronic component (120B/120A), which electrically connects the first metallic region (111) and a third metallic region (portion of 153 in the middle of 12A and 120B) on a second side of the lead frame facing away from the first cavity (upper side), wherein the second side is formed by a first outer side of the lead frame and the first side is formed by a side lying within the lead frame, and wherein the first cavity is formed by a cavity, which extends from the first side of the lead frame in a direction of a second outer side of the lead frame opposite the first outer side (note, the final structure does not require a cavity).
Regarding claim 19, Lim discloses the mold compound )113, [0080]) mechanically connects the first (111) and the at least one second metallic region (153) to one another (fig. 2).
Regarding claim 20, Lim discloses the mold compound (113) fills the first cavity (region where 113 is) and is substantially flush with the first side (bottom of 111/153/112) of the lead frame (fig. 2).
Regarding claim 22, Lim discloses the first (upper) and second sides (bottom) are formed by two opposite outer sides of the lead frame (111/153/112, fig. 2).
Regarding claim 23, Lim discloses the third metallic region (153 in the middle of 120A and 120B) is arranged on the mold compound (153 is arranged on a lower side 135) at a distance from the first metallic region (111, fig. 2).
Regarding claim 24, Lim discloses a fourth metallic region (112 on the right side of TH4) arranged at a distance from the third metallic region (153 in the middle of 120A and 120B); and a further optoelectronic component (120B) electrically connecting the third metallic region (153 in the middle of 120A and 120B) and the fourth metallic region (112 on the right side of TH4) to one another (via TH3 and TH4, fig. 2).
Regarding claim 25, Lim discloses the at least one electrical component (TH1) and the at least one optoelectronic component (120A) are connected in series with one another (direct connection, fig. 2).
Regarding claim 27, Lim discloses a first contact surface and a second contact surface on the second outer side of the lead frame opposite the second side, via which the optoelectronic device is electrically connectable (upper surfaces of 121 connected to 120A).
Regarding claim 29, as best the examiner is able to ascertain the claimed invention, Lim discloses (fig. 2 and related text) a method for manufacturing an optoelectronic device (100), the method comprising: providing a metallic substrate (111, 112,153) with at least one first cavity (region where R1, 113, and TH1-TH2 are formed ) on a first side of the substrate (bottom of (111, 112, 153); arranging at least one electrical component in the first cavity (TH1/TH2 serves as a conductive path for electrical signals between layers, hence electrical component); molding the at least one electrical component in the first cavity with a mold compound (113); creating at least one second cavity (region where 135 is formed) on a second side of the substrate opposite (upper side) the first side such that a first metallic region (the second 111 from the right, fig. 2) and at least one second metallic region (153 next to TH2) spaced therefrom are formed by the at least one first cavity (region where 113 is formed, note the final structure does not require a cavity) and the at least one second cavity (fig. 2), and wherein the at least one electrical component (TH1/TH2) electrically connects the first metallic region (the second 111 from the right) and the at least one second metallic region (153 next to TH2) to one another (via 121 and 122); arranging at least one optoelectronic component (120A/120B) on at least the first metallic region (111/153) such that the at least one optoelectronic component electrically connects the first metallic region and at least one of the second or a third metallic region (112 below R4) to one another (fig. 2); and applying a structured metallic layer (112 below 140 on the right) on the first side of the substrate (bottom), wherein the structured metallic layer (112) comprises at least one electrically insulated region (113 to the right 112).
Regarding claim 30, Lim discloses applying the structured metallic layer (112) is conducted before arranging the at least one optoelectronic component (120A/120B), and wherein the at least one optoelectronic component (120A/120B) is arranged on regions of the structured metallic layer (it appears from paragraph [0133] and [0134] 120A and 120B are connected to the frames in the end).
Regarding claim 31, Lim discloses the at least one optoelectronic component (120A/120B) electrically connects the first metallic region (111 and the third metallic region (112) to one another (via 120A and 120B), and wherein the third metallic region (112) is formed by a region of the structured metallic layer.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 21 and 26 are rejected under 35 U.S.C. 103 as being unpatentable over Lim.
Regarding claim 21, Lim does not disclose the electrical component comprises at least one of a series resistor, an ESD protection diode, an RFID chip, or an integrated circuit.
Replacing one device with another is routinely done in semiconductor device manufacturing.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to utilize appropriate component as claimed to meet the requirements of the particular design, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. /n re Aller, 105 USPQ 233.
Regarding claim 26, Lim does not disclose the at least one electrical component and the at least one optoelectronic component are connected in parallel with one another.
Wiring one device with another is routinely done in semiconductor device manufacturing.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to utilize appropriate wiring as claimed to meet the requirements of the particular design, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. /n re Aller, 105 USPQ 233.
Claim(s) 28 and 32-33 are rejected under 35 U.S.C. 103 as being unpatentable over Lim in view of Yu et al., WO 2008138183.
Regarding claim 28, Lim discloses the at least one electrical component electrically connects the first metallic region and the at least one second metallic region to one another.
However, Lim does not disclose the at least one electrical component electrically connects the first metallic region and the at least one second metallic region to one another via a bonding wire.
Yu discloses (fig. 7 and related text) an LED device (4) at least one electrical component (5) in the first cavity (fig. 7) comprises wire bonding (5) to provide light emitting diode having good heat dissipation effect and low manufacturing cost (refer to the description section).
Lim and Yu are analogous art because they both are directed to light emitting devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Lim with the specified features of Yu because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, on the effective filing date of the claimed invention, to modify Lim to include the wire bond taught by Yu in order to provide light emitting diode having good heat dissipation effect and low manufacturing cost (refer to the description section).
Regarding claim 32, Lim does not disclose the at least one electrical component in the first cavity comprises wire bonding.
Yu discloses (fig. 7 and related text) an LED device (4) at least one electrical component (5) in the first cavity (fig. 7) comprises wire bonding (5) to provide light emitting diode having good heat dissipation effect and low manufacturing cost (refer to the description section).
Lim and Yu are analogous art because they both are directed to light emitting devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Lim with the specified features of Yu because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, on the effective filing date of the claimed invention, to modify Lim to include the wire bond taught by Yu in order to provide light emitting diode having good heat dissipation effect and low manufacturing cost (refer to the description section).
Regarding claim 33, Lim does not disclose creating the at least one second cavity comprises an etching process.
Yu discloses creating the at least one cavity comprises an etching process (refer to the description of fig. 7).
Lim and Yu are analogous art because they both are directed to light emitting devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Lim with the specified features of Yu because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, on the effective filing date of the claimed invention, to modify Lim to include the etching process taught by Yu in order to provide light emitting diode having good heat dissipation effect and low manufacturing cost (refer to the description section).
Claim(s) 34 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lim in view of Cahill et al., WO 2015000594.
Regarding claim 34, as best the examiner is able to ascertain the claimed invention Lim does not disclose applying the structured metallic layer comprises at least one of sputtering, electrodeposition of a metallic layer or a photolithography process.
Cahill discloses (fig. 8 and related text) the process of fabricating metallic substrate/layer (leadframe) by electrodeposition in order to design die-to-die or die-to-substrate interconnects (refer to field of invention).
Lim and Cahill are analogous art because they both are directed to metallic substrate/leadframe use and one of ordinary skill in the art would have had a reasonable expectation of success to modify Lim with the specified features of Cahill because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, on the effective filing date of the claimed invention, to modify Lim to include the electrodeposition process taught by Cahill in order to design die-to-die or die-to-substrate interconnects (refer to field of invention).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SAMUEL A GEBREMARIAM whose telephone number is (571)272-1653. The examiner can normally be reached 8:30-4PM.
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/SAMUEL A GEBREMARIAM/Primary Examiner, Art Unit 2811
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