Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-5, 7 and 9 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by ”Hitachi” (WO 2020/213534. Examiner’s note: the citations are based on the English translation of Hitachi).
Regarding claim 1, Hitachi anticipates 1. An electronic control device comprising: a circuit board including first and second surfaces structured to be loaded with electronic components (Figs. 18-22, page 5, top; the substrate 30);
a first capacitor mounted to the first surface of the circuit board (Figs. 18-22, page 5, top; the capacitor 39 on the top of the substrate 30);
and a second capacitor mounted to the second surface of the circuit board and disposed oppositely to the first capacitor at least partially (Figs. 18-22, page 5, top; the capacitor 39 at the bottom of the substrate 30),
wherein the circuit board further includes: a first land disposed in the first surface of the circuit board and connected to the first capacitor (Figs. 18-22, page 5, top; pattern 34 has patterns PT1, PT2 and PT3);
a second land disposed in the second surface of the circuit board and connected to the second capacitor (Figs. 18-22, page 5, top; pattern 31 has patterns PT1, PT2 and PT3);
and a conduction passage establishing electrical continuity from the first land and the second land to a same power source line via the circuit board (Figs. 18-22, page 5, top; layer patterns 32 and 33 are connected to the battery and the respective patterns PT1, PT2 and PT3).
Regarding claim 2, Hitachi anticipates 2. The electronic control device as claimed in claim 1, wherein: the first capacitor includes a terminal connected to the first land and positioned apart from the conduction passage by a distance smaller than a diameter of the first capacitor (Figs. 18-22, page 5, top; the first capacitor 39 has a terminal positioned apart from the layer pattern 33 by a distance smaller than a diameter of the first capacitor);
and the second capacitor includes a terminal connected to the second land and positioned apart from the conduction passage by a distance smaller than a diameter of the second capacitor (Figs. 18-22, page 5, top; the second capacitor 39 has a terminal positioned apart from the layer pattern 32 by a distance smaller than a diameter of the second capacitor).
Regarding claim 3, Hitachi anticipates 3. The electronic control device as claimed in claim 1, wherein the conduction passage is positioned in the first land or the second land (Figs. 18-22, page 5, top; layer patterns 32 and 33 are positioned in the patterns 31 and 34 and the respective patterns PT1, PT2 and PT3).
Regarding claim 4, Hitachi anticipates 4. The electronic control device as claimed in claim 1, wherein the conduction passage is connected to the power source line formed in an inner layer of the circuit board (Figs. 18-22, page 5, top; patterns 32 and 33 are connected to the battery in an inner layer).
Regarding claim 5, Hitachi anticipates 5. The electronic control device as claimed in claim 1, wherein: the power source line is formed in the first surface of the circuit board (Figs. 18-22, page 5, top; patterns 32 and 33 are formed in the surface of the substrate 30);
and the second capacitor is connected to the power source line via the first land (Figs. 18-22, page 5, top; the second capacitor 39 is connected to the patterns 32 and 33 via the first land, see Fig. 22).
Regarding claim 7, Hitachi anticipates 7. The electronic control device as claimed in claim 2, wherein: the first land overlaps with the first capacitor; and the conduction passage faces the first capacitor (Figs. 18-22, page 5, top; the first land overlaps with the first capacitor; and the conduction passage faces the first capacitor, see Fig. 22).
Regarding claim 9, Hitachi anticipates 9. The electronic control device as claimed in claim 3, wherein the conduction passage is positioned in the first land and the second land (Figs. 18-22, page 5, top; layer patterns 32 and 33 are positioned in the patterns 31 and 34 and the respective patterns PT1, PT2 and PT3).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Hitachi in view of “Mikubo” (US 2002/0185718).
Regarding claim 6, Hitachi discloses the claimed invention as applied to claim 1, above.
Hitachi discloses the power source line is formed in the first surface of the circuit board (Figs. 18-22, page 5, top; patterns 32 and 33 are formed in the surface of the substrate 30).
Hitachi does not disclose the circuit board includes a through hole that is electrically discontinuous with a wiring with an anode potential of the circuit board; and the through hole is in thermal contact with a metallic member disposed on the second surface of the circuit board.
Mikubo discloses the circuit board includes a through hole that is electrically discontinuous with a wiring with an anode potential of the circuit board (Fig. 2, [0038]; heat radiating vias 9);
and the through hole is in thermal contact with a metallic member disposed on the second surface of the circuit board (Fig. 2, [0038]; heat radiating vias 9 are in thermal contact with the heat sink 10a).
It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to have constructed Hitachi’s electronic control device with Mikubo’s heat sink in order to reduce the mounting volume of a heat sink while providing satisfactory cooling capacity, as suggested by Mikubo at [0011].
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Hitachi in view of “Ito” (US 2009/0191730).
Regarding claim 8, Hitachi discloses the claimed invention as applied to claim 3, above.
Hitachi does not disclose the limitations of claim 8.
Ito discloses 8. The electronic control device as claimed in claim 3, wherein: the first land includes an opening extending through the first land; and the opening is positioned between a capacitor connection point of the first land connected to the first capacitor and a conduction passage connection point of the first land connected to the conduction passage (Fig. 14, [0135]; the soldering land 2 has a groove 61 positioned between a connection point and the through-hole 3).
It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to have constructed Hitachi’s electronic control device with Ito’s noise groove in order to prevent short circuiting since solder is sucked by the groove and does not flow into the through hole upper land, as suggested by Ito at [0135].
Claims 10 is rejected under 35 U.S.C. 103 as being unpatentable over Hitachi in view of “Kanezaki” (US 2016/0322951).
Regarding claim 10, Hitachi discloses the claimed invention as applied to claim 5, above.
Hitachi does not disclose the limitations of claim 10.
Kanezaki discloses 10. The electronic control device as claimed in claim 5, the electronic control device further comprising: a filter circuit component mounted to the first surface of the circuit board, wherein the second capacitor is connected to the filter circuit component via the conduction passage (Fig. 1, [0024] noise filter 1, the capacitor 21 is connected via a conduction passage).
It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to have constructed Hitachi’s electronic control device with Kanezaki’s noise filter in order to ensure a noise reduction effect even in a high-frequency band, as suggested by Kanezaki at [0005].
Conclusion
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/STANLEY TSO/Primary Examiner, Art Unit 2847
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