Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the “a second electrical connection (1212) between source regions (S) of the first and second ambipolar, gate all around, semiconductor-based transistors” must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-10 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation "the first-type material" in line 15. There is insufficient antecedent basis for this limitation in the claim. Claim 1 discloses “a first-type channel structure” but fails to explicitly disclose “a first type material”. The examiner is not clear if the "the first-type material" is referring back to the channel structure or another material layer.
Claims 11-19 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 11 recites the limitation "the first-type " in line 13. There is insufficient antecedent basis for this limitation in the claim. Claim 11 discloses “a first-type channel structure” but fails to explicitly disclose “a first type”. The examiner is not clear if the "the first-type" is referring back to the channel structure or another material layer.
Claims 11-19 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 11 discloses “a second electrical connection (1212) between source regions (S) of the first and second ambipolar, gate all around, semiconductor-based transistors”.
Specification [0023] describes Figure 12 illustrates an ambipolar GAA inverter.
Figure 12 does not show “a second electrical connection (1212) between source regions (S) of the first and second ambipolar, gate all around, semiconductor-based transistors”. Figure 12 shows an electrical connection between the gate regions.
The examiner is not clear if the electrical connection is between the source regions or the gate region.
Due to the two 112(b) rejections applied to claim 11 the examiner will not be applying prior art to claims 11-19 because there is a great deal of confusion as to the proper interpretations of limitations in the claims. MPEP 2173.06 II discloses “where there is a great deal of confusion and uncertainty as to the proper interpretation of the limitations of a claim, it would not be proper to reject such a claim on the basis of prior art. As stated in In reSteele, 305 F.2d 859, 134 USPQ 292 (CCPA 1962), a rejection under 35 U.S.C. 103 should not be based on considerable speculation about the meaning of terms employed in a claim or assumptions that must be made as to the scope of the claims.”
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 4, 5 and 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US 2019/0043997) in view of Dewey et al. (US 2020/0335501).
Lee disclose a substrate (120) (fig. 5); a first-type channel structure (131) located on the substrate, the first-type channel structure having a gate region (under gate 160), a source region (under 143), and a drain region (under 144); a second-type material (132) located on an entire external surface of the gate region (under 160)(fig. 5) of the first-type channel structure (131), but not on the source region (under 143) and the drain region (under 144); a dielectric material (151) the second-type material (132) on an entire external surface of the gate region; a gate electrode (160) located on the dielectric material (151); a source electrode (143) located on the source region; and a drain electrode (144) located on the drain region, wherein the first-type material is one of n-type [ 0071, n-type] and the second-type material is another of the p-type [0071, p-type].
Lee fails to disclose the gate all around transistor and the dielectric surrounding (the first and) second material.
Dewey et al. disclose the gate all around architecture [0001] in the gate around architecture the dielectric would surronde the channel structure.
The combination of Lee and Dewey would result in the dielectric surrounding channel structure (ie the first and second material).
The prior art included each element claimed, although not necessarily in a single prior art reference, with the only difference between the claimed invention and the prior art being the lack of actual combination of the elements in a single prior art reference.
One of ordinary skill in the art could have combined the elements as claimed by known methods (using a gate all around transistor), and that in combination, each element merely performs the same function as it does separately.
One of ordinary skill in the art would have recognized that the results of the combination were predictable (the GAA structure would enable a reduction in channel length [Dewey 0001]).
Regarding claim 4, Dewey disclose the gate region comprises: plural fins (nanowires/nanorod) extending from the source region to the drain region[0047].
Regarding claim 5, Dewey disclose each fin of the plural fins is a nanorod (nanowire) [0047].
Regarding claim 10, Lee disclose NiO [0072].
Allowable Subject Matter
Claim 20 is allowed.
Claims 2, 3, 6-9 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter, as the prior art of record fails to teach or suggest: the channel structure is made of a Ga2O3 material that includes a single layer of undoped Ga2O3 and a single layer of n- doped Ga2O3 (claims 2-3) each nanorod has a central region comprising the first-type material fully enclosed by the second-type material (claim 6) a flat layer of Ga2O3, wherein the plural fins are distributed on top of the flat layer of Ga2O3 so that dome-shaped fins and flat fins are formed, wherein each of the dome-shaped fins includes (1) a corresponding fin of the plural fins and (2) a portion of the flat layer of Ga2O3, and each flat fin includes another portion of the flat layer of Ga2O3 (claims 7-9) ambipolar, gate all around, semiconductor-based transistor, the method comprising: providing a first substrate; growing a first-type channel structure on the first substrate, the first-type channel structure having a gate region, a source region, and a drain region; etching the gate region to form plural fins depositing a second-type material on all but one portion of the gate region of the first-type channel structure, but not on the source region and the drain region; forming a dielectric material to surround the second-type material on all but one portion of the gate region depositing a gate electrode on the dielectric material, a source electrode on the source region, and a drain electrode on the drain region; forming a second substrate on the first-type channel structure; removing the first substrate; and depositing the second-type material on the one portion of the gate regionso that an entire external surface of the gate region are covered by the second-type material, wherein the channel structure is made of a Ga2O3 material.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRADLEY K SMITH whose telephone number is (571)272-1884. The examiner can normally be reached Monday-Friday, 10am-6pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Marlon Fletcher can be reached at 571-272-2063. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/BRADLEY SMITH/Primary Examiner, Art Unit 2817
Prosecution Insights