Office Action Predictor
Last updated: April 16, 2026
Application No. 18/691,889

CIRCUIT BOARD

Non-Final OA §102
Filed
Mar 14, 2024
Examiner
WILLIS, TREMESHA S
Art Unit
2847
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Kyocera Corporation
OA Round
1 (Non-Final)
78%
Grant Probability
Favorable
1-2
OA Rounds
2y 6m
To Grant
99%
With Interview

Examiner Intelligence

Grants 78% — above average
78%
Career Allow Rate
679 granted / 873 resolved
+9.8% vs TC avg
Strong +22% interview lift
Without
With
+22.5%
Interview Lift
resolved cases with interview
Typical timeline
2y 6m
Avg Prosecution
44 currently pending
Career history
917
Total Applications
across all art units

Statute-Specific Performance

§101
0.2%
-39.8% vs TC avg
§103
31.6%
-8.4% vs TC avg
§102
49.6%
+9.6% vs TC avg
§112
16.9%
-23.1% vs TC avg
Black line = Tech Center average estimate • Based on career data from 873 resolved cases

Office Action

§102
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1 – 2 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Matsumoto (Japanese Patent Publication No. 2007-96159). Regarding claim 1, in Figure 1, Matsumoto discloses a circuit board comprising: a first conductor (bottom layer 24); a second conductor (top layer 24); a transmission line (23) disposed between the first conductor and the second conductor; a first dielectric layer (12) disposed between the first conductor and the transmission line, the first dielectric layer comprising at least one first dielectric (paragraph [0010]); and a second dielectric layer (top layer 14) disposed between the second conductor and the transmission line, the second dielectric layer comprising at least one second dielectric (paragraph [0010]), wherein the second dielectric layer is thicker than the first dielectric layer (Figure 1), and a permittivity and/or a dielectric dissipation factor of the first dielectric is smaller than a permittivity and/or a dielectric dissipation factor of the second dielectric (insulating layers 12, 13 are made of a low dielectric loss material, insulating layer 14 is made of a higher dielectric loss material; claim 1, paragraph [0010]). Regarding claim 2, Matsumoto discloses wherein the second dielectric layer comprises a third conductor (22, Figure 1) different from the first conductor and the second conductor, at a position not overlapping the transmission line in a thickness direction of the circuit board. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to TREMESHA W BURNS whose telephone number is (571)270-3391. The examiner can normally be reached Monday-Friday 8am - 4:30 pm EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Timothy Thompson can be reached at (571) 272-2342. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. TREMESHA W. BURNS Primary Examiner Art Unit 2847 /TREMESHA W BURNS/Primary Examiner, Art Unit 2847
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Prosecution Timeline

Mar 14, 2024
Application Filed
Jan 09, 2026
Non-Final Rejection — §102
Mar 06, 2026
Interview Requested
Mar 12, 2026
Examiner Interview Summary
Mar 12, 2026
Applicant Interview (Telephonic)
Apr 01, 2026
Response Filed

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12604417
COPPER CLAD LAMINATE AND METHOD FOR PRODUCING THE SAME
2y 5m to grant Granted Apr 14, 2026
Patent 12604446
INTEGRATED DEVICE PACKAGE WITH REDUCED THICKNESS
2y 5m to grant Granted Apr 14, 2026
Patent 12604410
ELECTRONIC COMPONENT
2y 5m to grant Granted Apr 14, 2026
Patent 12598702
PRINTED CIRCUIT BOARD
2y 5m to grant Granted Apr 07, 2026
Patent 12598826
IMAGE SENSOR ASSEMBLY
2y 5m to grant Granted Apr 07, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
78%
Grant Probability
99%
With Interview (+22.5%)
2y 6m
Median Time to Grant
Low
PTA Risk
Based on 873 resolved cases by this examiner. Grant probability derived from career allow rate.

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