Prosecution Insights
Last updated: July 17, 2026
Application No. 18/691,902

CIRCUIT BOARD ASSEMBLY, DISPLAY MODULE AND MANUFACTURING METHOD THEREFOR, AND DISPLAY APPARATUS

Non-Final OA §102§112
Filed
Mar 14, 2024
Priority
Sep 17, 2021 — nonprovisional of PCTCN2021119177
Examiner
BURNS, TREMESHA WILLIS
Art Unit
2847
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
BOE Technology Group Co., Ltd.
OA Round
1 (Non-Final)
78%
Grant Probability
Favorable
1-2
OA Rounds
2m
Est. Remaining
95%
With Interview

Examiner Intelligence

Grants 78% — above average
78%
Career Allowance Rate
673 granted / 867 resolved
+9.6% vs TC avg
Strong +18% interview lift
Without
With
+17.7%
Interview Lift
resolved cases with interview
Typical timeline
2y 6m
Avg Prosecution
54 currently pending
Career history
887
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
47.2%
+7.2% vs TC avg
§102
49.9%
+9.9% vs TC avg
§112
1.8%
-38.2% vs TC avg
Black line = Tech Center average estimate • Based on career data from 867 resolved cases

Office Action

§102 §112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Claims 42 - 47 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Group, there being no allowable generic or linking claim. Election was made with traverse in the reply filed on May 8, 2026. The Restriction Requirement still stands for the reasons as set forth in the Requirement for Restriction/Election dated March 10, 2026. Drawings Figure 13 should be designated by a legend such as –Related Art-- because only that which is old is illustrated. See MPEP § 608.02(g). Corrected drawings in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. The replacement sheet(s) should be labeled “Replacement Sheet” in the page header (as per 37 CFR 1.84(c)) so as not to obstruct any portion of the drawing figures. If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. Claims 1 and 16 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. In particular, claim 1 recites “a change ratio of an overlapping state of the second bonding component in the first direction is less than 0.102%,” and claim 16 recites “a change ratio of an overlapping state, in the first direction, of a second conductive block corresponding to a middle position of the second bonding component is less than 0.050%.” The phrase “a change ratio” of an overlapping state of the second bonding component used in claims 1 and 16 is vague and unclear, thereby rendering the definition of the subject-matter of said claim unclear. First, it is unclear as to what is exactly considered a change ratio. Second, an overlapping state can only be defined by referring to two objects. In the above recitations, only a single object (second bonding component) is specified. Therefore, it is unclear how the overlapping state should be evaluated. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1, 2, 5, 7, 9, 13, 14, 16, 18, 19, 22 – 24, and 26 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Miyashita (U.S. Patent Publication No. 2019/124769). Regarding claim 1, in Figure 5, Miyashita discloses a circuit board assembly, comprising: a first circuit board (40; printed circuit board 40 includes a second board section 42) including at least one first bonding component (43), wherein a first bonding component includes a plurality of first conductive blocks (43b) sequentially arranged at intervals in a first direction; and at least one second circuit board (30; printed circuit board 30 includes a second board section 32) including at least one second bonding component (35), wherein a second bonding component includes a plurality of second conductive blocks (35b) sequentially arranged at intervals; and the plurality of second conductive blocks in the second bonding component are bonded to the plurality of first conductive blocks in the first bonding component in one-to-one correspondence (paragraph [0101]); wherein an expansion ratio of the first circuit board is less than an expansion ratio of the second circuit board (paragraph [0103]); and each second conductive block in the second bonding component overlaps with a first conductive block bonded thereto (Figure 5, paragraph [0101]), and a change ratio of an overlapping state of the second bonding component in the first direction is less than 0.102% (see 112 rejection above). Regarding claim 2, Miyashita discloses wherein the change ratio of the overlapping state of the second bonding component in the first direction is less than 0.059% (see 112 rejection). Regarding claim 5, Miyashita discloses wherein an overlapping width, in the first direction, of each second conductive block in the at least one second bonding component and a first conductive block bonded to the second conductive block is greater than or equal to two thirds of a width of the first conductive block (Figure 5). Regarding claim 7, Miyashita discloses wherein the first circuit board further includes: at least one first dummy bonding component, wherein in the first direction, the at least one first dummy bonding component and the at least one first bonding component are arranged side by side, and are alternately arranged from one side of the first circuit board to another side of the first circuit board; a first dummy bonding component in the at least one first dummy bonding component includes a plurality of first dummy conductive blocks sequentially arranged at intervals in the first direction (Figure 5). Regarding claim 9, Miyashita discloses wherein a center-to-center distance between two adjacent first conductive blocks in the first bonding component is in a range of 0.3 mm to 0.4 mm, inclusive; and a center-to-center distance between two adjacent second conductive blocks in the second bonding component is in a range of 0.3 mm to 0.4 mm, inclusive; a width of the first conductive block is in a range of 0.18 mm to 0.28 mm, inclusive; and/or a width of the second conductive block is in a range of 0.15mm to 0.2 mm, inclusive (Figure 5). Regarding claim 13, Miyashita discloses wherein a dimension of the first circuit board in the first direction is less than or equal to 350 mm; and a dimension of the second circuit board in the first direction is less than or equal to 200 mm (Figure 5). Regarding claim 14, Miyashita discloses a display module, comprising: a display panel; and at least one circuit board assembly each according to claim 1, wherein all second circuit boards of the at least one circuit board assembly are bonded to a same side of the display panel (Figure 2), wherein the display panel includes at least one third bonding component, and a third bonding component includes a plurality of third conductive blocks sequentially arranged at intervals in the first direction; and the at least one second circuit board further includes at least one fourth bonding component, a fourth bonding component includes a plurality of fourth conductive blocks sequentially arranged at intervals; and the plurality of fourth conductive blocks in the fourth bonding component are bonded to the plurality of third conductive blocks in the third bonding component in one-to-one correspondence; wherein an overlapping width, in the first direction, of each fourth conductive block in the at least one fourth bonding component and a third conductive block bonded to the fourth conductive block is greater than or equal to two thirds of a width of the third conductive block (Figures 2 and 5). Regarding claim 16, in Figure 5, Miyashita discloses a display module, comprising: a display panel (20, Figure 2); and a circuit board assembly (30, 40; Figure 2) located on a side of the display panel and bonded to the display panel; wherein the circuit board assembly includes: a first circuit board (30; printed circuit board 30 includes a first board section 31 and a second board section 32) including a plurality of first bonding components (35), wherein a first bonding component includes a plurality of first conductive blocks (35b) sequentially arranged at intervals in a first direction; and a plurality of second circuit boards (40; printed circuit board 40 includes a second board section 42); each including at least one second bonding component (43), wherein a second bonding component includes a plurality of second conductive blocks (43b) sequentially arranged at intervals; and the plurality of second conductive blocks in the second bonding component are bonded to the plurality of first conductive blocks in the first bonding component in one-to-one correspondence (paragraph [0101]); wherein an expansion ratio of the first circuit board is less than an expansion ratio of the second circuit board (paragraph [0103]); and each second conductive block in the second bonding component overlaps with a first conductive block bonded thereto (Figure 5, paragraph [0101]); and a change ratio of an overlapping state, in the first direction, of a second conductive block corresponding to a middle position of the second bonding component is less than 0.050% (see 112 rejection). Regarding claim 18, Miyashita discloses wherein the change ratio of the overlapping state, in the first direction, of the second conductive block corresponding to the middle position of the second bonding component is less than 0.028% (see 112 rejection). Regarding claim 19, Miyashita discloses wherein a change ratio of an overlapping state of the second bonding component in the first direction is less than 0.102% (see 112 rejection). Regarding claim 22, Miyashita discloses wherein a change ratio of an overlapping state of the second bonding component in the first direction is less than 0.028% (see 112 rejection). Regarding claim 23, Miyashita discloses wherein the second circuit board includes a first end bonded to the first circuit board and a second end connected to the display panel; and in a direction pointing from a bisecting plane of the first circuit board to an edge of the first circuit board in the first direction, as for all second circuit boards, deviations between midpoints of first ends and midpoints of respective second ends in the first direction gradually increase (Figure 5). Regarding claim 24, Miyashita discloses wherein in a same second circuit board, a midpoint of a first end is closer to the bisecting plane of the first circuit board than a midpoint of a second end (Figure 5). Regarding claim 26, Miyashita discloses wherein the display panel includes at least one third bonding component, and a third bonding component includes a plurality of third conductive blocks sequentially arranged at intervals in the first direction; and at least one second circuit board further includes at least one fourth bonding component, a fourth bonding component includes a plurality of fourth conductive blocks sequentially arranged at intervals; and the plurality of fourth conductive blocks in the fourth bonding component are bonded to the plurality of third conductive blocks in the third bonding component in one-to-one correspondence; wherein an overlapping width, in the first direction, of each fourth conductive block in the at least one fourth bonding component and a third conductive block bonded to the fourth conductive block is greater than or equal to two thirds of a width of the third conductive block (Figures 2 and 5). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to TREMESHA W BURNS whose telephone number is (571)270-3391. The examiner can normally be reached Monday-Friday 8am - 4:30 pm EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Timothy Thompson can be reached at (571) 272-2342. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. TREMESHA W. BURNS Primary Examiner Art Unit 2847 /TREMESHA W BURNS/Primary Examiner, Art Unit 2847
Read full office action

Prosecution Timeline

Mar 14, 2024
Application Filed
Jun 03, 2026
Non-Final Rejection mailed — §102, §112 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
78%
Grant Probability
95%
With Interview (+17.7%)
2y 6m (~2m remaining)
Median Time to Grant
Low
PTA Risk
Based on 867 resolved cases by this examiner. Grant probability derived from career allowance rate.

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