DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group II and Specie (a) directed to claims 20, 21, 32, 35, 50, 51, 60, 61 and 67 in the reply filed on 1/29/2026 is acknowledged.
Claims 1-2, 7-12, 15-16 and 18 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected subject matter.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 20, 21, 32, 35, 50 and 51 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Carey (US Patent 5091339).
Regarding claim 20 – Carey teaches a component carrier (figs. 6(a)-13), comprising: a design layer (14 [column 8 line 49] Carey states, “polyimide layer 14”) having a stamped surface profile (see stamping shown in figures 6(a) and 6(b) [column 6 lines 51-53] Carey states, “FIG. 6b plate 40 is stamped against polyimide layer 14 until plate surface 46 contacts top polyimide surface 48”); an at least partially electroplated metallic base structure (100 [column 9 & 8 lines 10, 31 & 22-26] Carey states, “seed layer 100…seed layer 80 of 2500 angstroms copper…After via regions 20 and channel regions 22 are formed there are many ways of depositing an electrically conducting layer into the via and channel including electrolytic deposition, electroless deposition, evaporation, sputtering, and squeegeeing”) in at least one indentation (20/22) of the profiled design layer (14); and an electroplated electroplating structure (104 [column 9 lines 12-13] Carey states, “electrically conductive layer 104 is electrolytically deposited over second seed layer 100”) in the at least one indentation (20/22) on or above the metallic base structure (100; claimed structure shown in figures 6(a)-13).
Additionally in accordance to MPEP 2113, the method of forming the device is not germane to the issue of patentability of the device itself. Therefore, this limitation has not been given significant patentable weight. Please note that even though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product, i.e. “metallic base structure” & “plating structure”, does not depend on its method of production, i.e. “electroplated”. In re Thorpe, 227 USPQ 964, 966 (Federal Circuit 1985).
Regarding claim 21 – Carey teaches the component carrier according to claim 20, comprising at least one of the following features:
wherein the electroplating structure (figs. 10c-13, 104) and the metallic base structure (100) form electrically conductive sub-structures of different depth or different length in the design layer (14; figure 11c shows the conductive sub-structures having different widths and depths);
wherein the electroplating structure and the metallic base structure form electrically conductive trace-type or via-type sub-structures;
wherein the electroplating structure and the metallic base structure form at least one electrically conductive sub-structure having a depth-to-diameter ratio of larger than 1;
wherein at least one sub-structure (fig. 10c, combination of layers 100 & 104) of the electroplating structure (104) and the metallic base structure (100) has tapering sidewalls (claimed structure show in figure 10a-10c);
wherein a roughness Ra of a surface of the design layer delimiting the surface profile is not more than 100 um wherein the design layer is arranged on an electrically conductive layer such that at least one surface portion of the electrically conductive layer is exposed with respect to the design layer at at least one of the indentations;
wherein the metallic base structure is arranged selectively on the at least one exposed surface portion of the electrically conductive layer and in the corresponding indentation of the design layer;
wherein at least a portion of the electroplating structure (fig. 10c, 104) is arranged on top of the metallic base structure (100);
wherein the metallic base structure comprises a bottom-sided sub-structure and a top-sided substructure; comprising an electrically conductive seed layer selectively lining indentations of the stamped design layer; comprising an electrically conductive seed layer at least partially between the metallic base structure and the electroplating structure.
Regarding claim 32 – Carey teaches the component carrier according to claim 20, comprising at least one of the following features:
wherein the component carrier (fig. 13) comprises a build-up (upper build-up 14) on one or both opposing sides of the profiled design layer (lower layer 14) with the metallic base structure (100) and the electroplating structure (104);
wherein the build-up (upper build-up 14) comprises at least one laminated printed circuit board layer stack (see stack shown in figure 13); comprising at least one component (120 [column 10 line 53-54] Carey states, “electrical component 120”) being electrically connected to the metallic base structure (100) and the electroplating structure (104).
Regarding claim 35 – Carney teaches the component carrier according to claim 20, comprising at least one of the following features:
further comprising a further design layer (figs. 12-13, upper layer 14) having a further stamped surface profile (upper layer 14 is a duplicate layer and will have the stamped surface profile as shown in figure 13), a further at least partially electroplated metallic base structure (100) in at least one further indentation (20/22) of the profiled further design layer (upper layer 14), and a further electroplated electroplating structure (104) in the at least one further indentation (20/22) on or above the further metallic base structure (100; claimed structure show in figure 14);
wherein the further profiled design layer (upper layer 14) with the further metallic base structure (100) and the further electroplating structure (104) are arranged on the profiled design layer (lower layer 14) with the metallic base structure (100) and the electroplating structure (104; claimed structure shown in figure 13);
wherein the further metallic base structure and the further electroplating structure are connected in a landless way with the metallic base structure and the electroplating structure; comprising a component mounted on the design layer by a connection structure arranged between the component and the design layer;
comprising two components arranged side-by-side at least partially on the design layer and being electrically coupled with each other by electrically conductive connection structures at or lateral from the design layer;
wherein at least one of the two components comprises pads having different pitch sizes being electrically coupled with the electrically conductive connection structures having different pitch sizes by connection structures having different dimensions;
wherein at least one first pad of the pads has a smaller pitch size than at least one second pad of the pads having a larger pitch size;
wherein the at least one first pad is electrically coupled with at least one first of the electrically conductive connection structures on the design layer; and
wherein the at least one second pad is electrically coupled with at least one second of the electrically conductive connection structures on a laminated printed circuit board layer stack apart from the design layer;
wherein the electroplating structure comprises three-dimensionally curved substructures;
wherein the indentations of the stamped design layer are at least partially filled with at least one wiring structure of the group consisting of:
a wiring structure having a bottom portion constituted by a bottom-sided portion of the metal base structure, wherein a top-sided portion of the metal base structure is formed directly on the bottom-sided portion, wherein a remaining volume of the wiring structure is lined with a portion of a seed layer covering a top surface of the metal base structure as well as an exposed sidewall of the design layer, and wherein a remaining volume of the wiring structure delimited by the portion of the seed layer is filled with at least a portion of the electroplating structure;
a wiring structure (see wiring structure shown in figure 10c) having a portion of a seed layer (80 [column 8 line 53-54] Carney states, “seed layer 80”) lining exposed sidewalls and an exposed bottom surface of the design layer (14), wherein a remaining volume of the wiring structure is filled with at least a portion of the electroplating structure (104);
a wiring structure having a bottom portion constituted by a bottom-sided portion of the metal base structure, wherein a top-sided portion of the metal base structure is formed directly on the bottom-sided portion, wherein a remaining volume of the wiring structure is lined with a portion of a seed layer covering a top surface of the metal base structure as well as an exposed sidewall and an exposed horizontal wall of the design layer, wherein a remaining volume of the wiring structure delimited by the portion of the seed layer is filled with at least a portion of the electroplating structure, and wherein the assigned indentation has a step;
configured as at least partially plate-shaped laminate-type component carrier; wherein at least a portion of the metallic base structure protrudes beyond the design layer and thereby forms at least one protruding metal structure for electric connection with an electronic periphery; wherein the electroplating structure protrudes beyond the design layer.
Regarding claim 50 – Carney teaches a component carrier (figs. 6(a)-13), comprising: an electrically conductive layer (100 [column 9 & 8 lines 10, 31 & 22-26] Carey states, “seed layer 100…seed layer 80 of 2500 angstroms copper…After via regions 20 and channel regions 22 are formed there are many ways of depositing an electrically conducting layer into the via and channel including electrolytic deposition, electroless deposition, evaporation, sputtering, and squeegeeing”); a stamped design layer (14 [column 8 & 6 lines 49 & 42-43] Carey states, “polyimide layer 14… Fig. 6a die stamp plate 40”) arranged on the electrically conductive layer (100) and having a surface profile with at least one indentation (20/22) so that at least one surface portion of the electrically conductive layer (100) is exposed with respect to the design layer (14); and an electroplated filling medium (104 [column 9 lines 12-13] Carey states, “electrically conductive layer 104 is electrolytically deposited over second seed layer 100”) at least partially filling the at least one indentation (20/22, claimed structure shown in figures 6(a)-13).
Regarding claim 51 – Carey teaches the component carrier according to claim 50, comprising at least one of the following features:
wherein the electroplated filling medium (fig. 10c, 104) comprises a metallic base structure (100) in the at least one indentation (20/22);
wherein the electroplated filling medium (fig. 10c, 104) comprises an electroplating structure (discussed in the rejection to claim 50 above) in the at least one indentation (20/22) on or above the metallic base structure (100);
comprising at least one of the following features:
wherein the design layer has an adhesion of more than 600 Nm;
wherein the design layer has a temperature resistance between 200°C and 300°C;
wherein the design layer comprises material of a flame retardancy class 4;
wherein the design layer comprises material having a glass-transition temperature between 120°C and 200°C;
wherein the design layer has a Modulus below a glass-transition temperature of 1000 MPa to 14000 MPa;
wherein the design layer has a Modulus above a glass-transition temperature of 60 MPa to 800 MPa;
wherein the design layer has a thermal expansion coefficient below a glass-transition temperature of 10 ppm/K to 40 ppm/K;
wherein the design layer has a thermal expansion coefficient above a glass-transition temperature of 50 ppm/K to 100 ppm/K;
wherein the design layer is formed with at least one of the following properties:
a fracture strain below a glass-transition temperature of at least 2%,
a chemical shrinkage below 3 %,a moisture absorption below 0,1%, and
a desmear rate of more than 0,006 g/min;
wherein the design layer comprises a fully cured polymer based on at least one of the following group comprising epoxies, acrylates, polyphenylenether, polyimide, polyamide, polyetheretherketon poly(p-phenylene ether) (PPE), Bisbenzocyclobutene (BCB), or Polybenzoxabenzole (PBO);
wherein the design layer comprises polymer- or oligomer-based building blocks, wherein at least one of the building blocks is based on one of the above-mentioned polymers;
wherein at least one of the building blocks has at least one functional group covalently bond to another one of the least one building block; wherein the at least one functional group is selected from one of the group consisting of:
a thiol group selected from the group of 3-mercaptopropionates, 3-mercaptoacetates, thioglycolates and alkylthiols, or
a double bond selected from the group of acrylates, methyl acrylates, vinyl ethers, allyl ethers, propenyl ethers, alkenes, dienes, unsaturated esters and allyl triazines, allyl isocyanates and N-vinyl amides;
wherein the design layer comprises a prepolymer having at least one photoinitiator, contained in an amount of 0.1 wt.% to 10 wt.%.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 60-61 is/are rejected under 35 U.S.C. 103 as being unpatentable over Carey in view of Nakai et al. (US PG. Pub. 2011/0300307).
Regarding claim 60 – Carey teaches the component carrier according to claim 20, wherein the design layer is a fully cured resin ([column 7 lines 51-52] Carey states, “photoimagible polyimide layers 14a and 14b are fully cured”), but fails to teach wherein the design layer further comprises filler particles in an amount of 1 wt.% to 10 wt.
Nakai teaches wherein the design layer (fig. 4, 106 [paragraph 0043] Carey states, “solder resist 106”) further comprises filler particles (62 [paragraph 0046] Nakai states, “Filler 62 is made of silica-type filler”) in an amount of 1 wt.% to 10 wt ([paragraph 0046] Naka states, “Solder resist 106 (insulation layer) is made by adding approximately 2-60 wt.% filler 62 to resin 61”).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the component carrier having a design layer as taught by Carey with the design layer further comprising filler particles in an amount of 1-10wt% as taught by Nakai because Nakai states, “the requirements of lower CTE (coefficient of thermal expansion) of solder resist 106 are satisfied in a printed wiring board.” [paragraph 0046]. Fillers, such as silica, within the design layer will help in thermal management and will improve the mechanical strength of the layer.
Regarding claim 61 – Carey in view of Nakai teach the component carrier according to claim 60, comprising at least one of the following features:
wherein the chloride content of the resin is below 30 ppm;
wherein the filler particles comprise inorganic fillers, wherein the inorganic fillers are in a crystalline state;
wherein the filler particles have a size of less than 0.1 pm;
wherein the filler particles (fig. 4, 62) comprise Talcum, Zeolite or fused SiO2 ([paragraph 0049] Nakai states, “As for silica, at least one from among ground silica, spherical silica, fused silica and crystalline silica is preferred to be used”);
wherein the filler particles are of plasma etchable material;
wherein the design layer (fig. 4, 106) comprises less than 95% filler particles ([paragraph 0046] Naka states, “Solder resist 106 (insulation layer) is made by adding approximately 2-60 wt.% filler 62 to resin 61”).
Claim(s) 67 is/are rejected under 35 U.S.C. 103 as being unpatentable over Carey in view of Morita et al. (US PG. Pub. 2015/0140346).
Regarding claim 67 – Carey teaches the component carrier according to claim 20, but fails to teach wherein the design layer has a viscosity of 0.01 Pas to 1 Pas.
Morita teaches wherein the design layer (fig. 1, 5 [paragraph 0057] Morita states, “cured coating film 5 made of the cured product of the above-described room-temperature-curable polyorganosiloxane composition of the present invention”) has a viscosity of 0.01 Pas to 1 Pas ([paragraph 0051] Morita states, “The obtained composition has 0.05 to 0.5 Pas viscosity at 23.degree. C”).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the component carrier having a design layer as taught by Carey with the design layer having a viscosity of 0.1 Pas to 1 Pas as taught by Morita because Morita states, “The room-temperature-curable polyorganosiloxane composition of the present invention has sufficiently low viscosity of 0.05 to 0.5 Pas at 23.degree. C. as described above, and thus has good coatability and can be applied as it is by an ordinary coating method without being diluted by a solvent. The coating film quickly cures at room temperature by coming into contact with the moisture in the air. The cured coating film has high hardness (Type A) of 60 or more and is excellent in electric and mechanical properties, especially in scratch resistance.” [paragraph 0053].
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to STEVEN T SAWYER whose telephone number is (571)270-5469. The examiner can normally be reached M-F 8:30 am - 5pm.
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/STEVEN T SAWYER/Primary Examiner, Art Unit 2847