Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claims 7 and 10 are objected to because of the following informalities:
Regarding claim 7, it appears that the portion "a width of an inner wall of the first portion gradually increases as it approaches the second portion" is left over from the original claim set and was likely intended to be lined through as the new amended claim is addressing similar subject matter but in greater detail. For the purposes of examination this section of text will be treated as if it was lined through.
Regarding claim 10, it appears that there is a typographical error and should read “wherein at least one of an upper OR side surfaces of the first pad includes a curved surface”, or similar, rather than “AND” as is currently written. For the purposes of examination, the claim will be treated with “or” rather than “and”.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-5, 7, 8, and 19 is/are rejected under 35 U.S.C. 102(a)(1) and (a)(2) as being anticipated by Nishida et al. (US Patent No. 9,538,650), hereinafter referred to as Nishida.
Regarding claim 1, Nishida teaches a circuit board comprising a first insulating layer (Fig. 5, base layer 120; Col. 3, line 13 - Col. 5, line 49 and Col. 6 line 56 - Col. 7 line 51); a first pad disposed on the first insulating layer (Fig. 5, connection terminal 132; Col. 3, line 13 - Col. 5, line 49 and Col. 6 line 56 - Col. 7 line 51); and a first protective layer disposed on the first insulating layer and having a first through hole vertically overlapping the first pad (Fig. 5, insulating layer 140, opening 150; Col. 3, line 13 - Col. 5, line 49 and Col. 6 line 56 - Col. 7 line 51), wherein an inner wall of the first through hole includes a contact surface in contact with a side surface of the first pad, and a non-contact surface located on the contact surface, and wherein the non-contact surface includes: a first portion connected to an upper end of the contact surface and having a first slope in a direction away from the first pad; and a second portion located on the first portion and having a second slope different from the first slope, wherein an upper end of the second portion of the non-contact surface is located higher than an upper surface of the first pad (Fig. 5; Col. 3, line 13 - Col. 5, line 49 and Col. 6 line 56 - Col. 7 line 51).
Regarding claim 2, Nishida further teaches at least a portion of the first portion of the non-contact surface overlaps the first pad in a horizontal direction (Fig. 5; Col. 3, line 13 - Col. 5, line 49 and Col. 6 line 56 - Col. 7 line 51).
Regarding claim 3, Nishida further teaches a width of the first portion in a horizontal direction is greater than a width of each of the second portion and the contact surface in the horizontal direction (Fig. 5; Col. 3, line 13 - Col. 5, line 49 and Col. 6 line 56 - Col. 7 line 51).
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Regarding claim 4, Nishida further teaches the first protective layer including a region overlapping the first portion of the non-contact surface in a vertical direction and gradually decreasing in thickness toward the side surface of the first pad (Fig. 5, insulating layer 140; Col. 3, line 13 - Col. 5, line 49 and Col. 6 line 56 - Col. 7 line 51).
Regarding claim 5, Nishida further teaches the slope of the second portion being closer to vertical than the slope of the first portion (Fig. 5; Col. 3, line 13 - Col. 5, line 49 and Col. 6 line 56 - Col. 7 line 51).
Regarding claim 7, Nishida further teaches a width in the horizontal direction between the first portion of the non-contact surface and a side surface of the first pad increases gradually along a vertical direction from the contact surface towards the second portion (Fig. 5; Col. 3, line 13 - Col. 5, line 49 and Col. 6 line 56 - Col. 7 line 51).
Regarding claim 8, Nishida further teaches an internal angle between the first portion and the lower surface of the first protective layer satisfies the range of 10 degrees to 70 degrees (Fig. 5, arbitrary point AP, normal line NL, parallel line PL, angle θ; Col. 3, line 13 - Col. 5, line 49 and Col. 6 line 56 - Col. 7 line 51).
Regarding claim 19, Nishida further teaches a semiconductor package comprising a first insulating layer (Figs. 1 & 2, base layer 120; Col. 3, line 13 - Col. 5, line); a first pad disposed on the first insulating layer (Figs. 1 & 2, connection terminal 132; Col. 3, line 13 - Col. 5, line 49); a first protective layer disposed on the first insulating layer and having a first through hole vertically overlapping the first pad (Fig. 1 & 2, insulating layer 140, opening 150; Col. 3, line 13 - Col. 5, line 49); and a semiconductor device disposed on the first pad (Fig. 2, semiconductor chip 20, connection terminal 132; Col. 3, line 13 - Col. 5, line 49), wherein an inner wall of the first through hole includes a contact surface in contact with a side surface of the first pad, and a non-contact surface located on the contact surface, and wherein the non-contact surface includes: a first portion connected to an upper end of the contact surface and having a first slope in a direction away from the first pad; and a second portion located on the first portion and having a second slope different from the first slope, wherein an upper end of the second portion of the non-contact surface is located higher than an upper surface of the first pad (Fig. 5, Col. 3, line 13 - Col. 5, line 49 and Col. 6 line 56 - Col. 7 line 51).
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Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 16-18 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nishida.
Regarding claim 16, Nishida teaches the circuit board of claim 1. Nishida does not explicitly teach a depression being provided between the first portion and the second portion that is recessed in an inner direction of the first protective layer away from the first pad. However, Nishida does teach that the shape of the second surface 142 may be changed freely so long as the angle relation disclosed is satisfied (Col. 7, lines 42-51). Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to have a depression being provided between the first portion and the second portion that is recessed in an inner direction of the first protective layer away from the first pad. For the purpose of increasing the surface area of the second surface to have better adhesion between said surface and the underfill, as recognized by Nishida.
Regarding claim 17, Nishida does not explicitly teach at least a portion of the depression being located higher than the upper surface of the first pad. However, Nishida does teach that the shape of the second surface 142 may be changed freely so long as the angle relation disclosed is satisfied (Col. 7, lines 42-51). Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to have at least a portion of the depression being located higher than the upper surface of the first pad. For the purpose of increasing the surface area of the second surface to have better adhesion between said surface and the underfill, as recognized by Nishida.
Regarding claim 18, Nishida does not explicitly teach at least a portion of the depression being located lower than the upper surface of the first pad. However, Nishida does teach that the shape of the second surface 142 may be changed freely so long as the angle relation disclosed is satisfied (Col. 7, lines 42-51). Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to have at least a portion of the depression being located lower than the upper surface of the first pad. For the purpose of increasing the surface area of the second surface to have better adhesion between said surface and the underfill, as recognized by Nishida.
Regarding claim 20, Nishida teaches the package of claim 19. However, Nishida does not explicitly teach a molding layer for molding the semiconductor device, wherein the first protective layer includes a depression provided between the first portion and the second portion and recessed in an inner direction of the first protective layer away from the first pad, and wherein the molding layer is provided to fill the depression.
However, Nishida does teach an underfill that is filled into a gap between the semiconductor chip and the second surface within the opening (Fig. 2, underfill 30, semiconductor chip 20, second surface 142, opening 150; Col. 5, lines 27 – 49) and that the shape of the second surface 142 may be changed freely so long as the angle relation disclosed is satisfied (Col. 7, lines 42-51).
Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to have a molding layer for molding the semiconductor device, wherein the first protective layer includes a depression provided between the first portion and the second portion and recessed in an inner direction of the first protective layer away from the first pad, and wherein the molding layer is provided to fill the depression. For the purpose of increasing the surface area of the second surface to have better adhesion between said surface and the underfill, as recognized by Nishida.
Claim(s) 6, 9 and 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nishida in view of Cho et al. (Pub. No. Us 20090027864 A1), hereinafter referred to as Cho.
Regarding claim 6, Nishida teaches the circuit board of claim 3. Nishida teaches the first pad including an overlapping portion overlapping the contact surface in a horizontal direction (Fig. 5, Col. 3, line 13 - Col. 5, line 49 and Col. 6 line 56 - Col. 7 line 51). However, Nishida does not explicitly teach a thickness of the overlapping portion satisfying a range of 50% to 98% of a thickness of the first pad.
Cho also teaches the first pad including an overlapping portion overlapping the contact surface in a horizontal direction (Fig. 4, pad 14, portion of the side 14b, solder resist 18, opening 20; ¶32-45). However, Cho also does not explicitly teach a thickness of the overlapping portion satisfying a range of 50% to 98% of a thickness of the first pad.
However, Cho does teach that the height of the opening in the solder resist for exposing a portion of the side of the pad, i.e. the thickness of the overlapping portion, can be determined in consideration of the adhesion to the pad, also with respect to the heat release characteristics, and the desired attachment area of the pad (¶32-45).
Nishida and Cho are analogous art as they are in the same field of endeavor of semiconductor devices. Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to have the overlapping region of Nishida and Cho have a thickness satisfying a range of 50% to 98% of a thickness of the first pad. For the purpose of optimizing the adhesion of the overlap area to the pad, the heat release characteristics, and/or the desired attachment area of the pad, as recognized by Cho.
Regarding claim 9, Nishida in view of Cho does not explicitly teach a vertical length between the lower surface of the first protective layer and an uppermost end of the first portion satisfying the range of 70% to 130% of a vertical length between a lower surface and an upper surface of the first pad.
However, Nishida does teach that the surface of the first protective layer can be freely shaped (Col. 7, lines 42-51).
Also, Cho does teach that the height of the opening in the solder resist for exposing a portion of the side of the pad can be determined in consideration of the adhesion to the pad, also with respect to the heat release characteristics, and the desired attachment area of the pad (¶32-45).
Nishida and Cho are analogous art as they are in the same field of endeavor of semiconductor devices. Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify Nishida in view of Cho such that a vertical length between the lower surface of the first protective layer and an uppermost end of the first portion satisfying the range of 70% to 130% of a vertical length between a lower surface and an upper surface of the first pad. For the purpose of optimizing various aspects of the device such as the adhesion of the overlap area to the pad, the heat release characteristics, and/or the desired attachment area of the pad, as recognized by Cho. And also optimizing aspects such as the suppression of voids in an underfill, adhesion of the surface to an underfill and/or the time required for filling an underfill, as recognized by Nishida.
Regarding claim 11, Nishida teaches a lower end of the first portion being located lower than the upper surface of the first pad (Figs. 1-5, Col. 3, line 13- Col. 4, line 67). However, Nishida in view of Cho does not explicitly teach an upper end of the first portion being located higher than the upper surface of the first pad.
However, Nishida does teach that the surface of the first protective layer can be freely shaped (Col. 7, lines 42-51).
Also, Cho teaches that the height of the opening in the solder resist for exposing a portion of the side of the pad can be determined in consideration of the adhesion to the pad, also with respect to the heat release characteristics, and the desired attachment area of the pad (¶32-45).
Nishida and Cho are analogous art as they are in the same field of endeavor of semiconductor devices. Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify Nishida in view of Cho such that an upper end of the first portion is located higher than the upper surface of the first pad. For the purpose of optimizing various aspects of the device such as the adhesion of the overlap area to the pad, the heat release characteristics, and/or the desired attachment area of the pad, as recognized by Cho. And also optimizing aspects such as the suppression of voids in an underfill, adhesion of the surface to an underfill and/or the time required for filling an underfill, as recognized by Nishida.
Claim(s) 10 and 13-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nishida in view of Nakamura (Pub. No. US 20150068791 A1).
Regarding claim 10, Nishida teaches the circuit board of claim 4. However, Nishida does not explicitly teach at least one of an upper or side surfaces of the first pad including a curved surface.
Nakamura teaches at least one of an upper or side surfaces of the first pad including a curved surface (Figs. 1A and 1B, pad 6; ¶40-46).
Nishida and Nakamura are in the same field of endeavor of semiconductor devices. Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify Nishida to incorporate the teachings of Nakamura to have the pads have at least one of an upper or side surfaces of the first pad including a curved surface. For the purpose of simplifying manufacturing, lower production costs, even solder flow, and/or stress uniformity to reduce solder cracking.
Regarding claim 13, Nishida teaches that the inner wall of the through hole can have various slopes (Figs. 1-5; ¶ Col. 3, line 13 - Col. 5, line 49 and Col. 6 line 56 - Col. 7 line 51). However, Nishida does not explicitly teach a second pad on the first insulating layer spaced apart from the first pad in a horizontal direction, wherein the first protective layer includes a second through hole overlapping the second pad in a vertical direction.
Nakamura teaches a second pad on the first insulating layer spaced apart from the first pad in a horizontal direction, wherein the first protective layer includes a second through hole overlapping the second pad in a vertical direction (Fig. 7D, pads 6, solder resist 4; ¶41-42, 44, 75-94).
Nishida and Nakamura are analogous art as they are in the same field of endeavor of semiconductor devices. Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify the opening teachings of Nishida with the multiple pads of Nakamura to have a second pad on the first insulating layer spaced apart from the first pad in a horizontal direction, wherein the first protective layer includes a second through hole overlapping the second pad in a vertical direction, wherein a slope of an inner wall of the second through hole is different from a slope of an inner wall of the first through hole. For the purpose of including multiple pads with different opening types such as SMD and NSMD for their respective advantages and disadvantages for different connection requirements, as recognized by Nakamura.
Regarding claim 14, Nishida does not explicitly teach a width of the inner wall of the second through hole is smaller than a width of the second pad.
Nakamura teaches a width of the inner wall of the second through hole is smaller than a width of the second pad (Figs. 1 & 7D, SMD structure 10, pads 6, solder resist 4; ¶41-42, 44, 75-94).
Nishida and Nakamura analogous art as they are in the same field of endeavor of semiconductor devices. Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify Nishida with the teachings of Nakamura to have a SMD type opening. For the purpose of improving adhesion of the pad to the board, as recognized by Nakamura.
Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nishida in view of Arai et al. (Pub. No. US 20200043841 A1, hereinafter referred to as Arai.
Regarding claim 12, Nishida teaches the circuit board of claim 4. However, Nishida does not teach a width in the horizontal direction between the second portion and a side surface of the first pad is equal along the vertical direction.
Arai teaches having a sidewall of the opening having a ninety-degree angle (opening 33, ¶24).
Nishida and Arai are analogous art as they are in the same field of endeavor of semiconductor devices. Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify Nishida with the teachings of Arai to have the second portion have a vertical sidewall at a ninety-degree angle, such that the horizontal direction between the second portion and a side surface of the first pad is equal along the vertical direction. For the purpose of optimizing protection of the pad, simplifying manufacturing, and/or lower production costs. Also, the use of certain manufacturing techniques, such as photolithography, as recognized by Arai.
Claim(s) 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nishida in view of Nakamura as applied to claim 13 above, and in further view of Lin et al. (Pub. No. US 20050023704 A1), hereinafter referred to as Lin.
Regarding claim 15, Nishida in view of Nakamura does not explicitly teach the second through hole including a plurality of sub-through holes overlapping one second pad in the vertical direction and spaced apart in the horizontal direction.
Lin teaches the second through hole including a plurality of sub-through holes overlapping one second pad in the vertical direction and spaced apart in the horizontal direction (Fig. 5A, ground plane 108, opening 102a; ¶4-13).
Nishida, Nakamura, and Lin are all analogous art as they are in the same field of endeavor of semiconductor devices. Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify Nishida in view of Nakamura to incorporate the teachings of Lin to have a second pad with a plurality of sub-through holes. For the purpose of mounting a chip onto a ground plane in a in a ball grid array (BGA) type package, as recognized by Lin.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Kohara et al. (Pub. No. US 20080061437 A1) and Tseng et al. (Pub. No. US 20220359446 A1).
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/FERNANDO L TOLEDO/Supervisory Patent Examiner, Art Unit 2897
/E.A.T./Examiner, Art Unit 2897
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