Election/Restriction
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention I, Claims 1-3, 5-6, 8-9, 18-22, 25, 29 in the reply filed on 07/09/2026 is acknowledged.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 29 is/are rejected under 35 U.S.C. 103 as being unpatentable over Brindle et al.(US 20210194478 A1, hereafter Brindle) in view of Hasegawa et al.(US 20030047782 A1, hereafter Hasegawa).
Regarding Claim 1, Brindle discloses:
A switch structure(Figs. 3-5), comprising:
A glass substrate(See paragraph 0079);
At least one switch sub-circuit(Fig. 5A) located on the glass substrate(See above), wherein the switch sub-circuit(Fig. 5A) comprises at least one switch unit(Fig. 5A [500]), the switch unit comprises a transistor(Fig. 5A [506]) and a resistor(Fig. 5A [510]); a gate of the transistor(Fig. 5A [506]) is electrically connected to the resistor(Fig. 5A [510]); the resistor(Fig. 5A [510]) is electrically connected to a power supply device(Fig. 5A [520]); a first electrode(Fig. 3C [304’]) of the at least one transistor(Fig. 5A [506]) is electrically connected to an in pad(Fig. 5A [502]), and a second electrode(Fig. 3C [306’]) of at least one transistor(Fig. 5A [506]) is electrically connected to an out pad(Fig. 5A [504]).
In the same field of endeavor, Hasegawa discloses a silicon material layer(Fig. 10 [108/110/109/111/102]) located on and bonded to a substrate(Fig. 10 [133]), wherein the silicon material layer(Fig. 10 [108/110/109/111/102]) comprises a conductive region(Fig. 10 [108]); a portion of the conductive region is configured to electrically connect the gate of the transistor(Fig. 10 [112]) and the resistor(Fig. 10 [114]), and an ion doping concentration of the conductive region is greater than or equal to 1 x 1018 cm-3(See paragraph 0072).
It would have been obvious to one of ordinary skill in the art at the time the application at hand was filed to modify the device disclosed by Brindle along the lines of Hasegawa. One might have been motivated to produce Brindle’s RF chip device with the configuration disclosed by Hasegawa as Brindle does not provide a specific structure by which the resistor is configured to be connected to the gate, thus requiring one of ordinary skill in the art to look further for a way by which to form these two components on the same chip. Performing this modification would have generated a predictable result in the creation of an embodiment of Brindle’s device.
Regarding Claim 29,
Brindle discloses their device as an radio frequency chip(See paragraph 0068).
Claim(s) 2-3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Brindle and Hasegawa, further in view of Matsumoto(US 20220285508 A1, hereafter Matsumoto).
Regarding Claim 2,
Neither Brindle nor Hasegawa teach or disclose at least one of the first electrode of the transistor, the second electrode of the transistor, and the gate of the transistor comprises an interdigital structure.
In the same field of endeavor, Matsumoto discloses at least one of the first electrode(Fig. 1 [19]) of the transistor(Fig. 1), the second electrode(Fig. 1 [24]) of the transistor(Fig. 1), and the gate(Fig. 1 [22]) of the transistor(Fig. 1) comprises an interdigital structure.
It would have been obvious to one of ordinary skill in the art at the time the application at hand was filed to further modify the device disclosed by Brindle and Hasegawa along the lines of Matsumoto. One might have been motivated to provide the electrodes as interdigital structures as to gain a greater active area of each of the source, gate, and drain electrodes, increasing the sensitivity of the respective components. Producing this device would have generated a predictable result in an embodiment of Brindle’s device with a source, drain, or gate electrode in accordance with the disclosure provided by Matsumoto.
Regarding Claim 3,
Neither Brindle nor Hasegawa teach or disclose the first electrode of the transistor, the second electrode of the transistor, and the gate of the transistor all comprise an interdigital structure, and an orthographic projection of the gate of the transistor partially overlaps with an orthographic projection of one of the first electrode of the transistor and the second electrode of the transistor on the glass substrate.
In the same field of endeavor, Matsumoto discloses the first electrode(Fig. 1 [19]) of the transistor(Fig. 1), the second electrode(Fig. 1 [24]) of the transistor(Fig. 1), and the gate(Fig. 1 [22]) of the transistor(Fig. 1) all comprise an interdigital structure, and an orthographic projection of the gate(Fig. 1 [22]) of the transistor(Fig. 1) partially overlaps with an orthographic projection of one of a first electrode(Fig. 1 [19]) and the second electrode(Fig. 1 [24]) of the transistor(Fig. 1) on the substrate.
It would have been obvious to one of ordinary skill in the art at the time the application at hand was filed to further modify the device disclosed by Brindle and Hasegawa along the lines of Matsumoto. One might have been motivated to provide the electrodes as interdigital structures as to gain a greater active area of each of the source, gate, and drain electrodes, increasing the sensitivity of the respective components. Producing this device would have generated a predictable result in an embodiment of Brindle’s device with a source, drain, or gate electrode in accordance with the disclosure provided by Matsumoto.
Claim(s) 5, 8-9, 18-22 is/are rejected under 35 U.S.C. 103 as being unpatentable over Brindle, Hasegawa, and Matsumoto, further in view of Lender et al.(US 20130321087 A1, hereafter Lender).
Regarding Claim 5,
Brindle, Hasegawa, and Matsumoto do not teach or disclose specifically the dimensions of their channel regions.
In the same field of endeavor, Lender discloses a channel structure with a length of 1 μm and a width of 12,800 μm(See paragraph 0027).
It would have been obvious to one of ordinary skill in the art to further modify the device disclosed by Brindle along the lines of Lender. One might have been motivated to provide a high width-to-length ratio as to be in accordance with the trend in the art of long channel structures in RF power devices. Performing this modification would have generated a predictable result in creating Brindle’s device with a specified channel dimension.
Regarding Claim 8, Brindle further discloses:
The Switch sub-circuit(Fig. 5A) comprises an in pad(Fig. 5A [502]) and an out pad(Fig. 5A [504]).
Regarding Claim 9, Brindle further discloses: The switch sub-circuit comprises a first switch unit(Fig. 5A [506/510/502/504]); the first switch unit comprises a first transistor(Fig. 5A [506]) and a first resistor(Fig. 5A [510]); and the power supply device(Fig. 5A [520]) comprises a first power supply device; and
A first electrode of the first transistor is electrically connected to the in pad(Fig. 5A [502]); a second electrode of the first transistor(Fig. 5A [506]) is electrically connected to the out pad(Fig. 5A [504]); a gate of the first transistor(Fig. 5A [506]) is electrically connected to a first terminal of the first resistor(Fig. 5A [510]); and the first power supply device(Fig. 5A [520]) is electrically connected to a ground terminal and a second terminal of the first resistor(Fig. 5A [510]), respectively.
Regarding Claim 18,
Brindle teaches a silicon material layer(Fig. 3C [304/312/306]) comprising a first semiconductor pattern(Fig. 3C [304/312/306]);
A gate insulating layer(Fig. 3C [110]) covering the silicon material layer(Fig. 3C [304/312/306]);
A gate layer(Fig. 3C [302]) located on a side of the gate insulating layer(Fig. 3C [110]) away from the glass substrate(See above) and comprising the gate of the transistor(Fig. 5A [506]);
A source/drain conductive layer(Fig. 3C [304/306]) and comprising the first electrode(Fig. 3C [304]) and the second electrode(Fig. 3C [306]) of the transistor(Fig. 5A [506]); and
Wherein the first semiconductor pattern(Fig. 3C [304/312/306]) comprises a semiconductor region(Fig. 3C [312]) and conductive regions(Fig. 3C [304/306]) located on two sides of the semiconductor region(Fig. 3C [312]); the first electrode(Fig. 3C [304]) is electrically connected to one of the conductive regions(Fig. 3C [304]) in the first semiconductor pattern(Fig. 3C [304/312/306]); the second electrode(Fig. 3C [306]) of the transistor(Fig. 5A [506]) is electrically connected to the other one(Fig. 3C [306]) of the conductive regions in the first semiconductor pattern(Fig. 3C [304/312/306]); the semiconductor region(Fig. 3C [312]) in the first semiconductor pattern(Fig. 3C [304/312/306]) serves as a channel region of the transistor(Fig. 5A [506]).
Brindle does not teach or disclose an interlevel dielectric covering the gate layer.
In the same field of endeavor, Matsumoto teaches an interlevel dielectric(Fig. 15C [26a]) covering the gate layer(Fig. 15C [14a]).
It would have been obvious to one of ordinary skill in the art at the time the application at hand was filed to modify the device disclosed by Brindle along the lines of Matsumoto. One might have been motivated to provide an interlevel dielectric in order to isolate the lower gate from components above the gate. Performing this modification would have generated a predictable result in the creation of an embodiment of Brindle’s device.
Furthermore, Brindle does not teach or disclose a second semiconductor pattern comprising a semiconductor region and conductive regions located on two sides of the semiconductor region, wherein the semiconductor region in the second semiconductor pattern serves as the resistor.
In the same field of endeavor, Hasegawa discloses a second semiconductor pattern(Fig. 14 [108/110]) comprising two conductive regions(Fig. 14 [108]) and a semiconductor region(Fig. 14 [110]), wherein the semiconductor region(Fig. 14 [110]) serves as a resistor.
It would have been obvious to one of ordinary skill in the art at the time the application at hand was filed to modify the device disclosed by Brindle along the lines of Hasegawa. One might have been motivated to produce Brindle’s RF chip device with the configuration disclosed by Hasegawa as Brindle does not provide a specific structure by which the resistor is configured to be connected to the gate, thus requiring one of ordinary skill in the art to look further for a way by which to form these two components on the same chip. Performing this modification would have generated a predictable result in the creation of an embodiment of Brindle’s device.
Regarding Claim 19,
Brindle discloses a first trace(Fig. 3C [302’]), a second trace(Fig. 5A See figure below) and a third trace(Fig. 5A [512]), wherein the first trace(Fig. 3C [302’]) is electrically connected to the third trace(Fig. 5A [512]); and
The first trace(Fig. 3C [302’]) is electrically connected to the gate(Fig. 3C [302]) of the transistor(Fig. 5A [506]).
Brindle does not teach or disclose the second and third traces being electrically connected to each of the conductive regions in the second semiconductor pattern. However, if one were to implement the resistors as disclosed by Hasegawa(See Fig. 14 [114]), one of ordinary skill in the art would understand the need for some method of linking the resistor’s conductive terminals with the rest of the circuit. Therefore, in the incorporation of the resistor, one of ordinary skill in the art would consider the possibility of using a trace to link the resistor with a power device as well as the gate of a transistor.
Regarding Claim 20,
Brindle does not teach or disclose the first electrode of the transistor comprises an interdigital structure or the limitations therein.
In the same field of endeavor, Matsumoto discloses:
A first electrode(Fig. 6 [12]) of a transistor(Fig. 6) comprises an interdigital structure;
The first electrode(Fig. 6 [12]) of the transistor(Fig. 6) comprises a first connection portion and N-2 first extension portions arranged in the same row; an extension direction of the first connection portion intersects with an extension direction of the first extension portions; an arrangement direction of the first extension portions is the same as the extension direction of the first connection portion; the first connection portion is located on the same side of each of the first extension portions and connects each of the extension portions together; N is a positive integer and is greater than or equal to 4; and
an orthographic projection of each of the first extension portions on the substrate at least partially overlaps with an orthographic projection of the first semiconductor pattern(Fig. 6 [11]) on the glass substrate.
It would have been obvious to one of ordinary skill in the art at the time the application at hand was filed to further modify the device disclosed by Brindle along the lines of Matsumoto. One might have been motivated to provide the electrodes as interdigital structures as to gain a greater active area of each of the source, gate, and drain electrodes, increasing the sensitivity of the respective components. Producing this device would have generated a predictable result in an embodiment of Brindle’s device with a source, drain, or gate electrode in accordance with the disclosure provided by Matsumoto.
Regarding Claim 21,
Brindle does not teach or disclose the second electrode of the transistor comprises an interdigital structure or the limitations therein.
In the same field of endeavor, Matsumoto discloses:
For at least one transistor(Fig. 6), a second electrode(Fig. 6 [24]) of the transistor(Fig. 6) comprises an interdigital structure;
the second electrode(Fig. 6 [24]) of the transistor(Fig. 6) comprises a second connection portion and N-3 second extension portions arranged in the same row; and extension direction of the second connection portion is the same as the extension direction of the first connecting portion; an arrangement direction of the second extension portions is the same as the arrangement direction of the first extension portions; the second connection portion is located on the same side of each of the second extension portions and connects each of the second extension portions together; and
an orthographic projection of each of the second extension portions on the substrate at least partially overlaps with the orthographic projection of the first semiconductor pattern(Fig. 6 [11]) on the substrate.
It would have been obvious to one of ordinary skill in the art at the time the application at hand was filed to further modify the device disclosed by Brindle along the lines of Matsumoto. One might have been motivated to provide the electrodes as interdigital structures as to gain a greater active area of each of the source, gate, and drain electrodes, increasing the sensitivity of the respective components. Producing this device would have generated a predictable result in an embodiment of Brindle’s device with a source, drain, or gate electrode in accordance with the disclosure provided by Matsumoto.
Regarding Claim 22,
Brindle does not teach or disclose the gate of the transistor comprises an interdigital structure or any limitations therein.
In the same field of endeavor, Matsumoto discloses:
A gate(Fig. 6 [22]) of the transistor(Fig. 6) comprises an interdigital structure;
The gate(Fig. 6 [22]) of the transistor(Fig. 6) comprises a third connection portion and N third extension portions arranged in the same row; an extension direction of the third connection portion intersects with an extension direction of the third extension portions; the third connection portion is located at the same side of each of the third extension portions and connects each of the third extension portions together; an orthographic projection of each of the third extension portions on the substrate at least partially overlaps with the orthographic projection of the first semiconductor pattern(Fig. 6 [11]) on the substrate; and an orthographic projection of the third connection portion on the substrate partially overlaps with the orthographic projections of all second extension portions on the glass substrate; and
Wherein the orthographic projections of the first extension portions, the third extension portions, and the second extension portions on the substrate are alternately arranged in sequence along the extension direction of the third connection portion.
It would have been obvious to one of ordinary skill in the art at the time the application at hand was filed to further modify the device disclosed by Brindle along the lines of Matsumoto. One might have been motivated to provide the electrodes as interdigital structures as to gain a greater active area of each of the source, gate, and drain electrodes, increasing the sensitivity of the respective components. Producing this device would have generated a predictable result in an embodiment of Brindle’s device with a source, drain, or gate electrode in accordance with the disclosure provided by Matsumoto.
See figure below for the respective connection/extension portions of the respective electrodes.
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Brindle, Hasegawa, and Matsumoto, further in view of Ping et al.(US 20220093608 A1, hereafter Ping).
Neither Brindle, Hasegawa, nor Matsumoto teach or disclose the silicon material layer comprises a monocrystalline silicon sub-layer.
In the same field of endeavor, Ping discloses a silicon material layer(Fig. 18 [225]) comprising a monocrystalline silicon sub-layer(See paragraph 0085).
It would have been obvious to one of ordinary skill in the art at the time the application at hand was filed to further modify the device disclosed by Brindle along the lines of Ping. One might have been motivated to produce the silicon material layer as a matter of routine experimentation, as Hasegawa’s polycrystalline silicon layer is only one of several known materials capable of being deposited as a semiconductor layer. Performing this modification would have generated a predictable result in the creation of an embodiment of Brindle’s device.
Claim(s) 25 is/are rejected under 35 U.S.C. 103 as being unpatentable over Brindle, Hasegawa, Matsumoto, and Lender, further in view of Herrault et al.(US 9825116 B1, hereafter Herrault).
Regarding Claim 25,
Brindle further discloses a DC pad(Fig. 4E [405]).
Brindle does not teach or disclose a coplanar waveguide.
In the same field of endeavor, Herrault discloses a coplanar waveguide(Fig. 3 [30]).
It would have been obvious to one of ordinary skill in the art at the time the application at hand was filed to arrive at the claimed limitation based on the prior art of Brindle, Hasegawa, and Herrault. In the integration of the features of a DC pad and a coplanar waveguide, one of ordinary skill in the art would have considered the provision of these components in a layer already intended to be part of the device, motivation to do so by the beneficial function of a waveguide in an RF circuit. Performing this modification would have generated a predictable result in the creation of an embodiment of Brindle’s device with a waveguide structure.
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891
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Above: Fig. 6 of Matsumoto with first, second, and third connection portions and first, second, and third extension portions.
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686
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Above: Fig. 5A of Brindle with second trace denoted by examiner.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Taddiken et al.(US 20180286941 A1) discloses an RF chip. Weyers et al.(US 20180096985 A1) discloses a polysilicon material layer connecting a resistor with a source/drain. Hayashi et al.(US 20050184349 A1) discloses an RF chip.
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/FERNANDO L TOLEDO/Supervisory Patent Examiner, Art Unit 2897
/MARSHALL MU-NUO HATFIELD/Examiner, Art Unit 2897
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