CTNF 18/695,006 CTNF 79224 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. This office action is in response to the application filed on 3/25/24. Currently, claims 1-10, 12-17, and 19-22 are pending. Information Disclosure Statement 06-52 The information disclosure statement (IDS) was submitted on 9/20/24. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. Specification 06-31 AIA The specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification. Claim Rejections - 35 USC § 102 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-15-aia AIA Claim(s) 1-10, 12-17, and 19-22 is/are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Luan et al. (US PGPub 2020/0027941, hereinafter referred to as “Luan”) . Luan discloses the semiconductor device and method as claimed. See figures 1-13 and corresponding text, where Luan teaches, in claim 1 , a display substrate, comprising a plurality of repetitive units, at least one of the repetitive units comprises a plurality of sub-pixels forming at least two pixel rows and at least two pixel columns (figure 1; [0043]), at least one of the sub-pixels comprises a pixel drive circuit (200) , a scan signal line (LScan1) configured to provide a scan signal to the pixel drive circuit (200) , and an auxiliary signal line ([0018]); the pixel drive circuit (200) comprises a storage capacitor (C1) and at least one transistor (T1) , wherein the storage capacitor (C1) at least comprises a first electrode plate, and the at least one transistor is connected with the first electrode plate through a connection electrode (figure 1; [0043-0046]); in a direction perpendicular to the display substrate, the display substrate comprises a first conductive layer disposed on a base substrate (11) , and a second conductive layer disposed on a side of the first conductive layer away from the base substrate (11) , the auxiliary signal line and the first electrode plate are disposed in the first conductive layer, the scan signal line (LScan1) and the connection electrode are disposed in the second conductive layer, an orthographic projection of the scan signal line on a plane of the base substrate (11) is within a range of an orthographic projection of the auxiliary signal line on the plane of the base substrate, and the scan signal line is lapped with the auxiliary signal line (figures 1-4 and 6-8; [0043-0058], [0074-0089]). Luan teaches, in claim 2 , wherein the storage capacitor further comprises a second electrode plate, and an orthographic projection of the second electrode plate on the plane of the base substrate is at least partially overlapped with an orthographic projection of the first electrode plate on the plane of the base substrate; the at least one transistor comprises a second transistor, the second transistor at least comprises a second gate electrode, the second gate electrode is connected with the second electrode plate through an electrode plate via, and an orthographic projection of the second gate electrode on the plane of the base substrate contains an orthographic projection of the electrode plate via on the plane of the base substrate (figures 1-4 and 6-8; [0043-0058], [0074-0089]). Luan teaches, in claim 3 , wherein the second transistor further comprises a second active layer, a first region of the second active layer is connected with a first power line via a power supply via, a second region of the second active layer is connected with the first electrode plate through a connection electrode, the first power line is configured to provide a power supply signal to the pixel drive circuit, and an orthographic projection of the first power line on the plane of the base substrate contains an orthographic projection of the power supply via on the plane of the base substrate (figures 1-4 and 6-8; [0043-0058], [0074-0089]). Luan teaches, in claim 4 , wherein second active layers of two adjacent sub-pixels in two adjacent repetitive units in a pixel row direction are of an interconnected integral structure, and/or, second active layers of two adjacent sub-pixels in two adjacent repetitive units in a pixel column direction are of an interconnected integral structure (figures 1-4 and 6-8; [0043-0058], [0074-0089]). Luan teaches, in claim 5 , wherein two adjacent sub-pixels in two adjacent repetitive units in a pixel row direction share the power supply via, and/or, two adjacent sub-pixels in two adjacent repetitive units in a pixel column direction share the power supply via (figures 1-4 and 6-8; [0043-0058], [0074-0089]). Luan teaches, in claim 6 , wherein the connection electrode comprises a first connection electrode connected with the first electrode plate, and a third connection electrode lapped with the first connection electrode; the pixel drive circuit further comprises a fifth connection electrode, and the fifth connection electrode is simultaneously connected with the second region of the second active layer and the third connection electrode through a first lap via; wherein a first dimension of the first lap via is greater than a second dimension of the first lap via, the first dimension is a dimension of the first lap via in a pixel row direction, and the second dimension is a dimension of the first lap via in a pixel column direction (figures 1-4 and 6-8; [0043-0058], [0074-0089]). Luan teaches, in claim 7 , wherein the power supply via and the first lap via are not on a straight line extending along the pixel row direction (figures 1-4 and 6-8; [0043-0058], [0074-0089]). Luan teaches, in claim 8 , wherein in the pixel column direction, the power supply via shared by two adjacent sub-pixels in two adjacent repetitive units is located between two adjacent first lap vias in two adjacent repetitive units (figures 1-4 and 6-8; [0043-0058], [0074-0089]). Luan teaches, in claim 9 , wherein the at least one transistor comprises a third transistor, the third transistor at least comprises a third active layer, a first region of the third active layer is connected with a compensation signal line through a compensation via, a second region of the third active layer is connected with the first electrode plate through a connection electrode, the compensation signal line is configured to provide a compensation signal to the pixel drive circuit, and an orthographic projection of the compensation signal line on the plane of the base substrate contains an orthographic projection of the compensation via on the plane of the base substrate (figures 1-4 and 6-8; [0043-0058], [0074-0089]). Luan teaches, in claim 10 , wherein in at least one repetitive unit, third active layers of two adjacent sub-pixels in a pixel row direction are of an interconnected integral structure, and/or, third active layers of two adjacent sub-pixels in a pixel column direction are of an interconnected integral structure; or, in at least one repetitive unit, two adjacent sub-pixels in a pixel row direction share the compensation via, and/or, two adjacent sub-pixels in a pixel column direction share the compensation via (figures 1-4 and 6-8; [0043-0058], [0074-0089]). Luan teaches, in claim 12 , wherein the connection electrode comprises a second connection electrode connected with the first electrode plate, and a fourth connection electrode lapped with the second connection electrode; the pixel drive circuit further comprises a sixth connection electrode, and the sixth connection electrode is simultaneously connected with the second region of the third active layer and the fourth connection electrode through a second lap via; wherein a third dimension of the second lap via is greater than a fourth dimension of the second lap via, the third dimension is a dimension of the second lap via in a pixel row direction, and the fourth dimension is a dimension of the second lap via in a pixel column direction (figures 1-4 and 6-8; [0043-0058], [0074-0089]). Luan teaches, in claim 13 , wherein the pixel drive circuit further comprises a first transistor, the first transistor at least comprises a first active layer, a first region of the first active layer is connected with a data signal line through a data via, the data signal line is configured to provide a data signal to the pixel drive circuit, and an orthographic projection of the data signal line on the plane of the base substrate contains an orthographic projection of the data via on the plane of the base substrate (figures 1-4 and 6-8; [0043-0058], [0074-0089]). Luan teaches, in claim 14 , wherein the pixel drive circuit at least comprises a first transistor and a third transistor, the first transistor at least comprises a first gate electrode, the third transistor at least comprises a third gate electrode, and the first gate electrode and the third gate electrode are respectively connected with the scan signal line through a gate connection electrode (figures 1-4 and 6-8; [0043-0058], [0074-0089]). Luan teaches, in claim 15 , wherein in at least one repetitive unit, gate connection electrodes, first gate electrodes, and third gate electrodes of two adjacent sub-pixels in a pixel column direction are disposed in a same layer, and are of an interconnected integral structure (figures 1-4 and 6-8; [0043-0058], [0074-0089]). Luan teaches, in claim 16 , wherein an orthographic projection of the gate connection electrode on the plane of the base substrate is at least partially overlapped with an orthographic projection of the scan signal line on the plane of the base substrate, and the gate connection electrode is connected with the scan signal line through a gate connection via (figures 1-4 and 6-8; [0043-0058], [0074-0089]). Luan teaches, in claim 17 , wherein in at least one repetitive unit, two adjacent sub-pixels in a pixel column direction share the gate connection electrode; or in at least one repetitive unit, two adjacent sub-pixels in a pixel column direction share the gate connection via (figures 1-4 and 6-8; [0043-0058], [0074-0089]). Luan teaches, in claim 19 , a display apparatus, comprising a display substrate according to claim 1 (figures 1-4 and 6-8; [0043-0058], [0074-0089]). Luan teaches, in claim 20 , a preparation method of a display substrate, wherein the display substrate comprises a plurality of repetitive units, at least one of the repetitive units comprises a plurality of sub-pixels forming at least two pixel rows and at least two pixel columns, at least one of the sub-pixels comprises a pixel drive circuit, a scan signal line configured to provide a scan signal to the pixel drive circuit, and an auxiliary signal line; the pixel drive circuit comprises a storage capacitor and at least one transistor, wherein the storage capacitor at least comprises a first electrode plate, and the at least one transistor is connected with the first electrode plate through a connection electrode; the preparation method comprises: forming a first conductive layer on a base substrate, and a second conductive layer disposed on a side of the first conductive layer away from the base substrate, wherein the auxiliary signal line and the first electrode plate are disposed in the first conductive layer, the scan signal line and the connection electrode are disposed in the second conductive layer, an orthographic projection of the scan signal line on a plane of the base substrate is within a range of an orthographic projection of the auxiliary signal line on the plane of the base substrate, and the scan signal line is lapped with the auxiliary signal line (figures 1-4 and 6-8; [0043-0058], [0074-0089]). Luan teaches, in claim 21 , wherein the forming the first conductive layer on the base substrate, and the second conductive layer disposed on the side of the first conductive layer away from the base substrate, comprises: depositing a first conductive thin film and a second conductive thin film sequentially; and using a patterning process with a half-tone mask to form the scan signal line and the auxiliary signal line through a first-time etching process, and to form the first electrode plate and the connection electrode through a second-time etching process (figures 1-4 and 6-8; [0043-0058], [0074-0089]). Luan teaches, in claim 22 , wherein the storage capacitor further comprises a second electrode plate, and an orthographic projection of the second electrode plate on the plane of the base substrate is at least partially overlapped with an orthographic projection of the first electrode plate on the plane of the base substrate; the preparation method further comprises: depositing a semiconductor thin film on a side of the second conductive layer away from the base substrate; and using a patterning process with a half-tone mask to form the second electrode plate through an etching process and a conductorization treatment process sequentially (figures 1-4 and 6-8; [0043-0058], [0074-0089]). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to STANETTA D ISAAC whose telephone number is (571)272-1671. The examiner can normally be reached M-F 10-6. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Leonard Chang can be reached at 571-270-3691. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /STANETTA D ISAAC/Examiner, Art Unit 2898 June 13, 2026 Application/Control Number: 18/695,006 Page 2 Art Unit: 2898 Application/Control Number: 18/695,006 Page 3 Art Unit: 2898 Application/Control Number: 18/695,006 Page 4 Art Unit: 2898 Application/Control Number: 18/695,006 Page 5 Art Unit: 2898 Application/Control Number: 18/695,006 Page 6 Art Unit: 2898 Application/Control Number: 18/695,006 Page 7 Art Unit: 2898 Application/Control Number: 18/695,006 Page 8 Art Unit: 2898 Application/Control Number: 18/695,006 Page 9 Art Unit: 2898 Application/Control Number: 18/695,006 Page 10 Art Unit: 2898 Application/Control Number: 18/695,006 Page 11 Art Unit: 2898
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