Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the
“the frame including a first upper pattern, a first lower pattern, and a dielectric sandwiched between the first upper pattern and the first lower pattern;
“a dielectric sandwiched between the first upper pattern and the first lower pattern; wherein the first upper pattern is electrically connected to the first terminal of the capacitor by a solder or electroconductive adhesive,
wherein the first lower pattern is electrically connected to the first upper pattern by a first via-hole through the dielectric and is electrically connected to the semiconductor die by a wiring” must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3 and 8-10 are rejected under 35 U.S.C. 103 as being unpatentable over Takagi (US 2012/0138954 A1) in view of Ishida et al. (US 6,621,162 B1).
Regarding independent claim 1: Takagi teaches (e.g., Figs. 1-3 and Fig. 10) a semiconductor device comprising:
a metal base ([0035]: 200);
a wall ([0035]-[0036]: 16) placed on the metal base,
the wall providing (16) an opening portion (Fig. 1C; [0033]-[0034]) inside of the wall;
a lid ([0033]: and [0039]: 10) placed on the wall ([0033]: and [0039]);
a semiconductor die ([0050]: 24) placed on the metal base,
the semiconductor die (24) being surrounded with the wall (16) so as to be placed in the opening portion, and
at least one capacitor ([0042]-[0044] and [0049]: C.sub.BR) outside of the lid (10),
wherein the capacitor includes a first terminal ([0042] and [0049]: terminal 41b of capacitor C.sub.BR) and a second terminal ([0042] and [0049]: opposite terminal of capacitor C.sub.BR);
wherein the first terminal of the capacitor (terminal 41b of capacitor C.sub.BR) is electrically connected to the semiconductor die ([0045]-[0051]: 24)
Takagi does not expressly teach at least one capacitor placed on a top surface of the wall.
Ishida teaches (e.g., Fig. 3) a semiconductor device comprising at least one capacitor (Col. 4; Lines 8- 38: #15) placed on a top surface of a wall (Col. 4; Lines 8-38: #12).
Note that Ishida also teaches that the capacitor (Col. 4; Lines 8- 38: #15) is outside the lid (Col. 4; Lines 8-50: #21).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, of Takagi, the at least one capacitor placed on a top surface of the wall, as taught by Ishida, for the benefits of ensuring that the capacitor is well supported and facilitating the interconnection with the active device; in addition, this configuration can reduce interference with lower devices.
Regarding claim 2: Takagi and Ishida teach the claim limitation of the semiconductor device according to claim1, on which this claim depends, further comprising:
Takagi as modified by Ishida teaches
a first upper pattern (Ishida: Col. 4, Lines 24-50: #18) placed between the capacitor and the top surface of the wall,
the first upper pattern (Ishida: Col. 4, Lines 24-50: #18) electrically connecting the first terminal of the capacitor (Ishida: #15) with the semiconductor die (Takagi: 24); and
a second upper pattern (Ishida: Col. 4, Lines 23-38: #17) placed on the top surface of the wall,
the second upper pattern electrically connecting the second terminal of the capacitor (Ishida: Col. 4, Lines 8-38: #15) with the metal base,
wherein the wall has a metal pattern (Ishida: Col. 4, Lines 8-38: #19) on a region inside the wall, and
wherein the first upper pattern includes the metal pattern of the wall (Ishida: Col. 4, Lines 8-38: #19),
the metal pattern (Ishida: Col. 4, Lines 8-38: #19 is electrically connected to a pad of the semiconductor die (Takashi: [0045]) by a wiring (Takagi: [0077]: 14),
wherein the pad of the semiconductor die is a drain pad (Takagi: [0077]: D1) of the semiconductor die.
Regarding claim 3: Takagi and Ishida teach the claim limitation of the semiconductor device according to claim 2, on which this claim depends, further comprising:
Takagi as modified by Ishida teaches
a third upper pattern (Ishida: Col. 5, Lines 1-9: left side 16) and a fourth upper pattern (Ishida: Col. 5, Lines 1-9: right side 16) each placed on the wall,
wherein the third upper pattern (Ishida: left side 16) is electrically connected to the first upper pattern (Ishida: 18),
wherein the fourth upper pattern (Ishida: right side 16) is electrically connected to the second upper pattern (Ishida: 17) and is electrically connected to the metal base (Takada: 200) via a via-hole (Ishida: Col. 4, Lines 8-38; see 19).
Regarding claim 8: Takagi and Ishida teach the claim limitation of the semiconductor device according to claim 1, on which this claim depends,
wherein the semiconductor die includes a substrate (Takagi: [0080]: 110) and a nitride semiconductor layer (Takagi: [0080]: 112) disposed on a surface of the substrate.
Regarding claim 9: Takagi and Ishida teach the claim limitation of the semiconductor device according to claim 1, on which this claim depends, further comprising:
an impedance matching circuit (Takagi: [0051]-[0052]: 18) placed on the metal base, the impedance matching circuit being surrounded with the wall (Takagi: 16) and electrically connected to the semiconductor die (Takagi: 24);
wherein the lid (Takagi: 10) covers the semiconductor die (Takagi: 24) and the impedance matching circuit (Takagi: 18).
Regarding claim 10: Takagi and Ishida teach the claim limitation of the semiconductor device according to claim 1, on which this claim depends,
wherein the at least one capacitor (Ishida: Col. 4, Lines 8-38: #15) includes a first capacitor (Ishida: Col. 4, Lines 8-38: left side #15) and a second capacitor (Ishida: Col. 4, Lines 8-38: right side #15),
wherein the first capacitor (Ishida: Col. 4, Lines 8-38: left side #15) is placed on a first side portion of the wall (Ishida: left side of 12), and the second capacitor (Ishida: Col. 4, Lines 8-38: right side #15) is placed on a second side portion of the wall (Ishida: right side of 12), opposite to the first side portion.
Claims 4-5 are rejected under 35 U.S.C. 103 as being unpatentable over Takagi (US 2012/0138954 A1) in view of Ishida et al. (US 6,621,162 B1) as applied above and further in view of Viswanathan et al. (US 2016/0172318A1).
Regarding claim 4: Takagi and Ishida teach the claim limitation of the semiconductor device according to claim 1, on which this claim depends. a frame (Takagi: [0033]: 14a) placed on a surface of the wall.
Takagi as modified by Ishida does not expressly teach that
the frame including a first upper pattern, a first lower pattern, and a dielectric sandwiched between the first upper pattern and the first lower pattern;
wherein the first upper pattern is electrically connected to the first terminal of the capacitor by a solder or electroconductive adhesive,
wherein the first lower pattern is electrically connected to the first upper pattern by a first via-hole through the dielectric and is electrically connected to the semiconductor die by a wiring.
Viswanathan teaches (e.g., Figs. 1-4 and 6) a semiconductor device comprising
a frame ([0033], [0042] and [0047]: 420/308/303); the frame including
a first upper pattern ([0033], [0042] and [0047]: left side 303), a first lower pattern ([0033], [0042] and [0047]: left side 420), and a dielectric ([0033], [0042] and [0047]: left side 308) sandwiched between the first upper pattern and the first lower pattern;
wherein the first upper pattern is electrically connected to a first terminal of a capacitor ([0048]: 314) by a solder or electroconductive adhesive ([0048] and [0058]: solder),
wherein the first lower pattern (left side 420) is electrically connected to the first upper pattern (left side 303) by a first via-hole through the dielectric ([0070]: PCB is a printed circuit board; it is understood that a PCB includes vias for interconnection, thus this meets the claim limitation requirements) and is electrically connected to a semiconductor die ([0043]: 320) by a wiring ([0047]-[0049]: 312).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to include in the device of Takagi as modified by Ishida, the frame including a first upper pattern, a first lower pattern, and a dielectric sandwiched between the first upper pattern and the first lower pattern; wherein the first upper pattern is electrically connected to the first terminal of the capacitor by a solder or electroconductive adhesive, wherein the first lower pattern is electrically connected to the first upper pattern by a first via-hole through the dielectric and is electrically connected to the semiconductor die by a wiring, as taught by Viswanathan, for the benefits of reducing signal interference during device in operation and further protecting the integrated circuit device included in the packaging.
Regarding claim 5: Takagi and Ishida and Viswanathan teach the claim limitation of the semiconductor device according to claim 4, on which this claim depends,
wherein the frame further includes a second upper pattern (Viswanathan: [0047] right side 305) and a second lower pattern (Viswanathan: [0047]: right side 320), the second upper pattern and the second lower pattern sandwiching the dielectric (Viswanathan: [0047]: right side 308) therebetween,
wherein the second upper pattern is electrically connected to the second terminal of the capacitor (Viswanathan: [0048]: 314) by a solder or electroconductive adhesive (Viswanathan: [0048] and [0058]: solder),
and the second lower pattern (Viswanathan: left side 420) is electrically connected to the second upper pattern by a second via-hole through the dielectric (Viswanathan: ([0070]: PCB is a printed circuit board; it is understood that a PCB includes vias for interconnection, thus this meets the claim limitation requirements) and is connected to the metal base (Viswanathan: [0047]: 306).
Claims 6-7 are rejected under 35 U.S.C. 103 as being unpatentable over Takagi (US 2012/0138954 A1) in view of Ishida et al. (US 6,621,162 B1) as applied above and further in view of Asano et al. (US 2010/0208442 A1).
Regarding claim 6: Takagi and Ishida teach the claim limitation of the semiconductor device according to claim 1, on which this claim depends,
wherein the metal base is made of a high thermal conductivity material of 50 W/(m . K) or more (Takagi: [0034]-[0035]: Copper has a thermal conductivity of approximately 401 W/(m·K) at room temperature (20°C); thermal conductivity of copper meets the claim limitation requirements).
Takagi as modified by Ishida does not expressly teach that the wall is made of a glass-microfiber-reinforced resin or a fluorocarbon resin.
Asano teaches (e.g., Fig. 1) a semiconductor device comprising a wall made of a glass-microfiber-reinforced resin or a fluorocarbon resin ([0042]: a fluorocarbon resin).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to include in the device of Takagi as modified by Ishida, the wall made of a fluorocarbon resin, as taught by Asano, for the benefits of combining durability, chemical inertness and thermal stability, making them a preferred choice for demanding environments where long-term performance and low maintenance are essential.
Regarding claim 7: Takagi and Ishida teach the claim limitation of the semiconductor device according to claim 6, on which this claim depends,
wherein the high thermal conductivity material includes a copper or copper alloy (Takagi: [0034]-[0035]: copper or copper alloy).
Claims 12 and 14-16 are rejected under 35 U.S.C. 103 as being unpatentable over Takagi (US 2012/0138954 A1) in view of Ishida et al. (US 6,621,162 B1) as applied above and further in view Stoneham et al. (US 2006/0001129 A1).
Regarding claim 12: Takagi and Ishida teach the claim limitation of the semiconductor device according to claim 1, on which this claim depends,
wherein the semiconductor die includes a first semiconductor die (Takagi: 24) and
the opening portion includes a first opening portion (Takagi: [0034]: 19a) and a second opening portion (Takagi: [0034]: 19b),
wherein the first semiconductor die (Takagi 24) is placed inside the first opening. and
Takagi as modified by Ishida does not expressly
a second semiconductor die, wherein the second semiconductor die is placed inside the second opening.
Stoneham teaches a semiconductor device comprising a second semiconductor die ([0016]: right side semiconductor die 42), wherein the second semiconductor die is placed inside a second opening ([0013]: 26).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to include in the device of Takagi as modified by Ishida, the second semiconductor die, wherein the second semiconductor die is placed inside the second opening, as taught by Stoneham, for the benefits of protecting enclosed circuit assemblies from environmental and electromagnetic influences and/or isolating the enclosed circuit assemblies (Stoneham: [0008]).
Regarding claim 14: Takagi, Ishida and Stoneham teach the claim limitation of the semiconductor device according to claim 12, on which this claim depends,
wherein the lid includes a first lid (Stoneham: [0008]-[0009], [0013] and [0019]: left side lid 22 in region 14) and a second lid (Stoneham: [0008]-[0009], [0013] and [0019]: right side lid 22 in region 14), and
the at least one capacitor includes a first capacitor, a second capacitor, a third capacitor and a fourth capacitor (Ishida: Fig. 3; Col. 4; Lines 8- 38: from left to right a first capacitor, a second capacitor, a third capacitor and a fourth capacitor 15),
wherein the first capacitor and the second capacitor are located outside the first lid (Ishida: Fig. 3; Col. 4; Lines 8- 38: from left to right a first capacitor, a second capacitor 15), and
the third capacitor and the fourth capacitor are located outside of the second lid (Ishida: Fig. 3; Col. 4; Lines 8- 38: from left to right a third capacitor and a fourth capacitor 15).
Regarding claim 15: Takagi, Ishida and Stoneham teach the claim limitation of the semiconductor device according to claim 12, on which this claim depends, further comprising:
a first impedance matching circuit and a second impedance matching circuit (Takagi: [0042] and [0051]-[0052]: 17 and 18),
wherein the lid covers the first semiconductor die (Takagi: [0051]-[0052]: 24), the second semiconductor die (Takagi: [0051]-[0052] and [0076]: plurality of FET cells FET 1), the first impedance matching circuit (Takagi: [0042] and [0051]-[0052]: 17), and the second impedance matching circuit (Takagi: [0042], [0051]-[0052]: 18).
Regarding claim 16: Takagi, Ishida and Stoneham teach the claim limitation of the semiconductor device according to claim 12, on which this claim depends,
wherein the at least one capacitor includes a first capacitor and a second capacitor each placed on the wall,
wherein the first capacitor and the second capacitor (Ishida: Fig. 3; Col. 4; Lines 8- 38: from left to right first capacitor, a second capacitor 15) are located outside the lid.
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Takagi (US 2012/0138954 A1) in view of Ishida et al. (US 6,621,162 B1) and Stoneham et al. (US 2006/0001129 A1) as applied above and further in view Schultz et al. (US 2019/0140598 A1).
Regarding claim 13: Takagi, Ishida and Stoneham teach the claim limitation of the semiconductor device according to claim 12, on which this claim depends, further comprising:
a first impedance matching circuit (Takagi: [0051]-[0052]: 17 and
a second impedance matching circuit (Takagi: [0042] and [0051]-[0052]: 18),
wherein the lid includes a first lid (Takagi: 10) and
a second lid (Stoneham: [0008]-[0009], [0013] and [0019]: right side lid 22 in region 14),
wherein the first lid (Takagi: 10) covers the first semiconductor die (Takagi: 24) and the first impedance matching circuit (Takagi: [0051]-[0052]: 17) which are placed inside the first opening,
and the second lid covers the second semiconductor die (Stoneham: right side 22).
Takagi as modified by Ishida and Stoneham does not expressly teach that the second impedance matching circuit is placed inside the second opening.
Schultz teaches (e.g., Fig. 6) a semiconductor device comprising
a first semiconductor die ([0110]: left side 640) connected to a first impedance matching circuit ([0110]: left side impedance matching circuit 650),
a second semiconductor device ([0110]: right side 640) connected to a second impedance matching circuit ([0100]: right side impedance matching circuit 650).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to include in the device of Takagi as modified by Ishida and Stoneham, the second semiconductor device connected to the second impedance matching circuit, and arrive at “the second impedance matching circuit is placed inside the second opening”, since the second semiconductor device is placed inside the second opening, so as to provide a more robust protecting from environmental and electromagnetic influences.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HERVE-LOUIS Y ASSOUMAN whose telephone number is (571)272-2606. The examiner can normally be reached M-F: 08:30 AM-5:30 PM.
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/HERVE-LOUIS Y ASSOUMAN/ Examiner, Art Unit 2812
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