DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 1/28/2025 was filed. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1 is/are rejected under 35 U.S.C. 102a1 as being anticipated by Yuan (US 2021/0407384)
Regarding claim 1.
Yuan teaches:
A display panel (fig 16:200; [para 0112]), comprising a plurality of sub-pixel units (fig 13,14; [para 0091]), each of the sub-pixel units provided with a light-emitting device (fig 13:20; [para 0092]) and a pixel driving circuit (fig 13:10; [para 0094]) connected to the light-emitting device (fig 13:20; [para 0092]), wherein the pixel driving circuit (fig 13:10; [para 0094]) comprises: a switch transistor (fig 13:T2; [para 0096,0097]), a first electrode of the switch transistor (fig 13:T2; [para 0096,0097]) connected to a first data signal line (fig 13:Vdata; [para 0046]) and a second electrode of the switch transistor (fig 13:T2; [para 0096,0097]) connected to a first node (fig 13:N2; [para 0076]);
a driving transistor (fig 13:T0; [para 0091]), a first electrode of the driving transistor connected to the first node (fig 13:N2; [para 0076]), a second electrode of the driving transistor (fig 13:T0; [para 0091]) connected to a second node (fig 13:N3; [para 0076]), and a driving gate of the driving transistor (fig 13:T0; [para 0091]) connected to a third node (fig 13:N1; [para 0076]);
a compensation transistor (fig 13:15,T3; [para 0064]), a first electrode of the compensation transistor (fig 13:15,T3; [para 0064]) connected to the third node (fig 13:N1; [para 0076]), and a second electrode of the compensation transistor (fig 13:T3; [para 0064]) connected to the second node (fig 13:N3; [para 0076]);
a first reset transistor (fig 13:16,T5; [para 0065,0066]), a first electrode of the first reset transistor (fig 13:16,T5; [para 0065,0066]) connected to a first reset signal line (fig 13:Vref; [para 0065]), and a second electrode of the first reset transistor (fig 13:16,T5; [para 0065,0066]) connected to the first node (fig 13:N2; [para 0076]);
and a first capacitor (fig 13:C2; [para 0088]), a first plate of the first capacitor (fig 13:C2; [para 0088]) connected to the first reset signal line (fig 13:Vref; [para 0065]), and a second plate of the first capacitor (fig 13:C2; [para 0088]) connected to a first high potential line (fig 13:PVDD; [para 0083]).
Claim(s) 20 is/are rejected under 35 U.S.C. 102a1 as being anticipated by Yuan (US 2021/0407384)
Regarding claim 20.
Yuan teaches
A display device, comprising a display panel (fig 16:200; [para 0112]), the display panel (fig 16:200; [para 0112]) comprising a plurality of sub-pixel units (fig 13,14; [para 0091]), each of the sub-pixel units (fig 13,14; [para 0091]) provided with a light-emitting device (fig 13:20; [para 0092]) and a pixel driving circuit (fig 13:10; [para 0094]) connected to the light-emitting device (fig 13:20; [para 0092]), wherein the pixel driving circuit (fig 13:10; [para 0094]) comprises: a switch transistor (fig 13:T2; [para 0096,0097]), a first electrode of the switch transistor (fig 13:T2; [para 0096,0097]) connected to a first data signal line (fig 13:Vdata; [para 0046]) and a second electrode of the switch transistor (fig 13:T2; [para 0096,0097]) connected to a first node (fig 13:N2; [para 0076]);
a driving transistor (fig 13:T0; [para 0091]), a first electrode of the driving transistor (fig 13:T0; [para 0091]) connected to the first node (fig 13:N2; [para 0076]), a second electrode of the driving transistor (fig 13:T0; [para 0091]) connected to a second node (fig 13:N3; [para 0076]), and a driving gate of the driving transistor (fig 13:N3; [para 0076]) connected to a third node (fig 12:N1; [para 0076]);
a compensation transistor (fig 13:15,T3; [para 0064]), a first electrode of the compensation transistor (fig 13:15,T3; [para 0064]) connected to the third node (fig 12:N1; [para 0076]), and a second electrode of the compensation transistor (fig 13:15,T3; [para 0064]) connected to the second node (fig 13:N3; [para 0076]); a first reset transistor (fig 13:16,T5; [para 0065,0066]), a first electrode of the first reset transistor (fig 13:16,T5; [para 0065,0066]) connected to a first reset signal line (fig 13:Vref; [para 0065]), and a second electrode of the first reset transistor (fig 13:16,T5; [para 0065,0066]) connected to the first node (fig 13:N2; [para 0076]);
and a first capacitor (fig 13:C2; [para 0088]), a first plate of the first capacitor (fig 13:C2; [para 0088]) connected to the first reset signal line (fig 13:Vref; [para 0065]), and a second plate of the first capacitor (fig 13:C2; [para 0088]) connected to a first high potential line (fig 13:PVDD; [para 0083]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Rejection Note: Italicized and struck through claim limitations indicate limitations that are not explicitly disclosed in the primary reference, but disclosed in the secondary reference(s).
Claim(s) 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yuan (US 2021/0407384) as applied to claim 1 and further in view of Shang (US 2022/0336540)
Regarding claim 2.
Yuan teaches the display panel according to claim 1, further
Yuan teaches:
a base substrate (fig 14; [para 0103]);
a first gate layer (fig 14:g1,m1; [para 0104]), disposed on one side of the base substrate (fig 14; [para 0103]);
a second gate layer (fig 14:g2,m2; [para 0103]), disposed on one side of the first gate layer (fig 14:g1,m1; [para 0104]) away from the base substrate (fig 14; [para 0103]);
a third gate layer (fig 14:g3,m3; [para 0104]), disposed on one side of the second gate layer (fig 14:g2,m2; [para 0103]) away from the first gate layer (fig 14:g1,c23; [para 0104]);
a first source-drain layer (fig 14:m4; [para 0104]), disposed on one side of the third gate layer (fig 14:g3,m3; [para 0104]) away from the second gate layer (fig 14:g2,m2; [para 0103]);
wherein the first plate (fig 14:c11,m1; [para 0104]) is disposed in at least one of the first gate layer (fig 14:g1,m1; [para 0104])
Yuan does not teach second and third source drain layers
Shang teaches:
and a second source-drain layer (fig 13a:964; [para 0076]), disposed on one side of the first source-drain layer (fig 13a:963; [para 0076]) away from the third gate layer (fig 13a:203g; [para 0289]);
wherein the first plate (fig 5,13a:Cst1; [para 0295]) is disposed in at least one of the first gate layer (fig 13a:203g; [para 0295]) and the first source-drain layer (fig 13a:963; [para 0076]), and the second plate (fig 13a:Cst2,9130; [para 0198]) disposed in the second source-drain layer (fig 13a:964; [para 0076]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide second and third source drain layers in order to provide more layers of planarization and enable a flatter surface (paragraph 58) and to enable more complex wiring and interconnection patterns (paragraph 5).
Allowable Subject Matter
Claims 3 through 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 3, the prior art does not teach in combination with other elements of the claim, display panel, comprising a plurality of sub-pixel units comprising a pixel driving circuit comprising, the second source-drain layer comprises a plurality of first high potential lines arranged along a first direction and extending in a second direction; the first source-drain layer comprises a first sub-part of the first plate, one end of the first sub-part is electrically connected to the first reset signal line, and another end of the first sub-part is connected to an active part of the first reset transistor; an orthographic projection of the first sub-part projected on the second source-drain layer is at least partially located within the first high potential line, and an angle between the first direction and the second direction is greater than 0 degrees and less than or equal to 90 degrees.
Regarding claim 9, the prior art does not teach in combination with other elements of the claim, a display panel, comprising a plurality of sub-pixel units comprising a pixel driving circuit comprising,
a storage capacitor comprising a third plate and a fourth plate, wherein the third plate is connected to the third node, and the fourth plate is connected to the first high potential line; a second reset transistor, a first electrode of the second reset transistor is connected to the second reset signal line, and a second electrode of the second reset transistor is connected to an anode of the light-emitting device; a third reset transistor, wherein a first electrode of the third reset transistor is connected to the third reset signal line, and a second electrode of the third reset transistor is connected to the third node; a first light-emitting transistor, wherein a first electrode of the first light-emitting transistor is connected to the first high potential line, and a second electrode of the first light-emitting transistor is connected to the first node, and a gate of the first light-emitting transistor is connected to a light-emitting signal line; a second light-emitting transistor, wherein a first electrode of the second light-emitting transistor is connected to the second node, a second electrode of the second light-emitting transistor is connected to an anode of the light-emitting device, and a gate of the second light-emitting transistor is connected to the light-emitting signal line; and a boost capacitor, comprising a fifth plate and a sixth plate, wherein the fifth plate is connected to the third node, and the sixth plate is connected to the second scan signal line.
Conclusion
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/D.J.G/Examiner, Art Unit 2817
/Kretelia Graham/Supervisory Patent Examiner, Art Unit 2817
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