Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This action is responsive to the application No. 18/695,915 filed on March 27, 2024.
Information Disclosure Statement
Acknowledgement is made of Applicant’s Information Disclosure Statement (IDS) form PTO-1449. These IDS has been considered.
Claim Objections
4. Claims 1, 5-10, 13-18, 20 are objected to because of the following informalities: In the following, the claims should be recited to avoid indefiniteness due to lack of antecedent basis, and/or smooth flow of claim languages/phrases:
1. (Currently Amended) A digital information processing device, comprising:
a soft material including a plurality of electrically conductive and electrically non- conductive regions, wherein the soft material having a shape configured to transform from an uncompressed configuration to fully compact configurations under an applied load,
wherein the plurality of electrically conductive regions forms electrical networks that are in a closed or open state dependent upon the applied load acting on the soft material.
5. (Currently Amended) The digital information processing device according to claim 2, wherein a digital output sequence of the electrical networks corresponds to an output of the preferred Boolean algebra function or arithmetic expression.
6. (Currently Amended) A digital information processing device, comprising:
a non-electrically conductive soft material substrate having a matrix of unit cells stacked together; and
traces of electrically-conductive soft material coated on a surface and/or applied inside some of the matrix of unit cells;
wherein a configuration of the matrix of unit cells transforms into at least one fully compact self-contact configuration under an applied sideway load to compress the matrix of unit cells;
wherein the traces of electrically-conductive soft material form an electrical network in the fully compact self-contact configuration.
7. (Currently Amended) The digital information processing device according to claim 6, wherein a cross-section geometry of the digital information processing device is constant, wherein a response to applied loads uniformly deforms each stacked unit cell, resulting in fully compact configurations.
8. (Currently Amended) The digital information processing device according to claim 6, wherein the matrix of unit cells are connected together in a configuration of repeating stacked layers with periodic gaps and without discontinuities, wherein the at least one fully compact self-contact configuration includes one fully compact self-contact configuration, wherein the electrical network is an electrically conductive network in the fully compact self-contact configuration.
9. (Currently Amended) The digital information processing device according to claim 6, wherein the electrical network includes variable open and closed states according to
10. (Currently Amended) The digital information processing device according to claim 9, wherein the variable open and closed states of the electrical network are identical to
13. (Currently Amended) The digital information processing device according to claim 11, wherein the matrix of unit cells are connected together in a configuration of stacked elemental switches with periodic gaps and with discontinuities, at least one fully compact self-contact configuration includes four fully compact self-contact configurations corresponding to 4 buckling modes due to a combination of clockwise rotation and counterclockwise rotation of rotating layers, 2-bit binary inputs are based on (counter) clockwise assignment of binary digital bits for the rotating layers, the four fully compact self-contact configurations correspond to binary digital outputs, the binary digital outputs correspond to variable open or closed states of the electrical network representative of Boolean operations of logic gates.
14. (Currently Amended) The digital information processing device according to claim 11, wherein the matrix of unit cells are stacked together in columns and rows with periodic gaps and with discontinuities, a rotating layer alternate and numbers of the rotating layers being equal to numbers of inputs, numbers of columns being equal to numbers of minterms in the standard sum of product (SSoP) formulations, the switches in the same column connected in series and the columns connected in parallel.
15. (Currently Amended) The digital information processing device according to claim 6, wherein a material result from a shear stress, mechanical force, mechanical pressure, thermomechanical loads, optomechanical loads, chemomechanical loads, electroactive material loads, and/or other body forces.
16. (Currently Amended) The digital information processing device according to claim 6, wherein the non-electrically conductive soft material substrate and/or the traces of electrically conductive soft material
17. (Currently Amended) A digital information processing device, comprising:
a soft material including a soft material substrate and an electrically conductive soft material layer disposed on or in the substrate, wherein the soft material responds to applied stresses by creating an electrical network of the electrically conductive soft material layer, the electrical network having a variable connecting configuration, and
wherein the variable connecting configuration of the electrical network is in agreement with a preferred Boolean function or arithmetic expression.
18. (Currently Amended) The digital information processing device according to claim 17, wherein the applied stresses exerted in the soft material result from a shear stress, mechanical force, mechanical pressure, thermomechanical loads, optomechanical loads, chemomechanical loads, electroactive material loads, and/or other body forces.
20. (Currently Amended) The digital information processing device according to claim 17, wherein the digital information processing device is a logic gate or an integrated circuit or a storage device.
Appropriate corrections are needed.
Claim Rejections - 35 USC § 102
5. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
6. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
7. Claims 1-3, 5-12, 15-20 are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Helou et al. “Digital Logic Gates in Soft, conductive mechanical metamaterials,” Nature Communications 12.1 (2021), published 12 March 2021 (12.03.2021).
Regarding independent claim 1, Helou et al. discloses a digital information processing device, comprising (Figs. 1 (a)-(b)):
a soft material including a plurality of electrically conductive and electrically non- conductive regions (C2 unit cell comprises conductive Ag-TPU trace and non-conductive regions), the soft material having a shape configured to transform from an uncompressed configuration (see Fig. 1(b)) to fully compact configurations (see Fig. 1 (b)) under an applied load,
wherein the electrically conductive regions form electrical networks (see Fig. 1(a) and Fig. (b)) that are in a closed or open state (see Fig. 1 (b) open when LED lights “off” or closed when LED lighs “ON”) dependent upon the applied load acting on the soft material (uncompressed or compacted).
Regarding claim 2, Helou et al. discloses wherein, the closed or open state of the electrical networks (see Figs. 1(a)/(b)) corresponds to digital logic functioning (like as buffer and NOT, see Fig. 3 (d), (e)),
wherein the digital logic functioning (0 or 1) is in agreement with a preferred Boolean algebra function (Boolean logic operations, see page 1) or arithmetic expression.
Regarding claim 3, Helou et al. discloses wherein, the closed or open state of the electrical networks (see Figs. 1(a)/(b)) is representative of Boolean operations BUFFER and NOT (page 5, column 2, lines 3-6),
whereby the shape transformation of the soft material closes or opens the electrical network of Boolean operations BUFFER (see Fig. 3(d)) and NOT (see Fig. (e)) according to the preferred Boolean function (Boolean logic operations, see page 1).
Regarding claim 5, Helou et al. discloses wherein (Fig. 4), a digital output sequence of the electrical networks (AND gate, OR gate or Buffer or NOT) corresponds to an output of the preferred Boolean function (see logic gates) or arithmetic expression.
Regarding independent claim 6, Helou et al. discloses a digital information processing device (all logic gates shown in Figs. 1 (a)/(b), 4), comprising:
a non-electrically conductive soft material substrate having a matrix of unit cells stacked together (C2 unit cell comprises non-conductive regions); and
traces of electrically-conductive soft material coated on a surface and/or applied inside some of the unit cells (C2 unit cell comprises conductive Ag-TPU trace/regions);
wherein the configuration of the matrix (see Fig, 4(b)) transforms into at least one fully compact self-contact configuration (a) under an applied sideway load to compress the matrix; wherein the traces form an electrical network (AND gate, OR gate or Buffer or NOT, see Fig. 4) in the fully compact self-contact configuration.
Regarding claim 7, Helou et al. discloses wherein (Figs. 1 (a-b), 4), a cross-section geometry (size or shape) of the device is constant,
wherein response to applied loads uniformly deforms each stacked unit cell (see Fig. (b)), resulting in fully compact configurations.
Regarding claim 8, Helou et al. discloses wherein (Figs. 1 (a-b), 4), the unit cells are connected together in a configuration of repeating stacked layers with periodic gaps and without discontinuities (see Fig. 4, no discontinuity shown), wherein the at least one fully compact self-contact configuration (Fig. 4(a)) includes one fully compact self-contact configuration, wherein the electrical network (AND gate, OR gate or Buffer or NOT) is an electrically conductive network in the fully compact self-contact configuration.
Regarding claim 9, Helou et al. discloses wherein (Figs. 1 (a-b), 4), the electrical network (AND gate, OR gate or Buffer or NOT) includes variable open and closed states according to the distinct fully compact configurations of the stacked unit cells (see Fig. 4).
Regarding claim 10, Helou et al. discloses wherein (Figs. 1 (a-b), 4), the variable open and closed states of the electrical network (AND gate, OR gate or Buffer or NOT) are identical to the digital representations of output signals obtained from a Boolean algebra function (A.B=QAND) or arithmetic expression, and
wherein inputs (A, B, see Fig. 4) agree with the associated digitized inputs to the Boolean function (A.B=QAND) or arithmetic expression.
Regarding claim 11, Helou et al. discloses wherein (Fig. 4), the electrical network is an elemental switch (c), the at least one fully compact self-contact configuration includes two fully compact self-contact configurations (d) includes two fully compact self-contact configurations, the two fully compact self-contact configuration (d) correspond to binary digital outputs (QNAND), the binary digital outputs correspond to an open or closed state of the elemental switch.
Regarding claim 12, Helou et al. discloses wherein (Fig. 3), the elemental switch is a BUFFER (see Fig. 3 (d)) or NOT switch (see Fig. 3 (e)).
Regarding claim 15, Helou et al. discloses wherein (Fig. 4), the stresses exerted in the material result from shear stress (modes are realized by the specific vector combination of shear and uniaxial stresses applied to the top metamaterial surface, page 5, column 1), mechanical force, mechanical pressure, thermomechanical loads, optomechanical loads, chemomechanical loads, electroactive material loads, and/or other body forces.
Regarding claim 16, Helou et al. discloses wherein (Figs. 4-5), the soft material substrate (see page 7, column 1) and/or the electrically conductive soft material layer are composed of a material that intrinsically responds to applied fields, including light, thermal gradients, mechanical load, electromagnetic waves, acoustic waves, humidity gradients, pH gradients, and/or other applied fields.
Regarding independent claim 17, Helou et al. discloses a digital information processing device, comprising (Fig. 4):
a soft material including a soft material substrate (see page 7, column 1, wherein the elastomeric metamaterial substrates are fabricated by casting liquid urethane rubber in a two-part mold) and an electrically conductive soft material layer (conductive ink, page 7, column 1) disposed on or in the substrate, the soft material responds to applied stresses by creating an electrical network (see Fig. 4) of the electrically conductive soft material layer (digital logic gates in soft material, see Fig. 4), the electrical network having a variable connecting configuration (AND, NAND, OR, NOR, XOR, XNOR), and
wherein the connecting configuration of the electrical network is in agreement with a preferred Boolean function (such as A.B=AB, see Fig. 4) or arithmetic expression (page 5, column 2).
Regarding claim 18, Helou et al. discloses wherein (Fig. 4), the stresses exerted in the soft material result from shear stress (modes are realized by the specific vector combination of shear and uniaxial stresses applied to the top metamaterial surface, page 5, column 1), mechanical force, mechanical pressure, thermomechanical loads, optomechanical loads, chemomechanical loads, electroactive material loads, and/or other body forces.
Regarding claim 19, Helou et al. discloses wherein (Figs. 4-5), the soft material substrate (see page 7, column 1) and/or the electrically conductive soft material layer are composed of a material that intrinsically responds to applied fields, including light, thermal gradients, mechanical load, electromagnetic waves, acoustic waves, humidity gradients, pH gradients, and/or other applied fields.
Regarding claim 20, Helou et al. discloses wherein (Fig. 4), the device is a logic gate (page 5, lines 6-9) or an integrated circuit or a storage device.
Allowable Subject Matter
8. Claims 4, 13, 14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 4 is allowed because all prior arts to include those on record either singularly or in combination fail to anticipate or render obvious of the digital information processing device, comprising:
…. digitized mechanical input conditions for the electrical networks are in the form of shear stress, mechanical force, mechanical pressure, thermomechanical loads, optomechanical loads, chemomechanical loads, electroactive material loads, and other body forces to yield the fully compact configurations of the device.
Claim 13 is allowed because all prior arts to include those on record either singularly or in combination fail to anticipate or render obvious of the digital information processing device, comprising:
…. the unit cells are connected together in a configuration of stacked elemental switches with periodic gaps and with discontinuities, at least one fully compact self-contact configuration includes four fully compact self-contact configurations corresponding to 4 buckling modes due to a combination of clockwise rotation and counterclockwise rotation of rotating layers, 2-bit binary inputs are based on (counter)clockwise assignment of binary digital bits for the rotating layers, the four fully compact self-contact configurations correspond to binary digital outputs, the binary digital outputs correspond to variable open or closed states of the electrical network representative of Boolean operations of logic gates.
Claim 14 is allowed because all prior arts to include those on record either singularly or in combination fail to anticipate or render obvious of the digital information processing device, comprising:
…. the unit cells are stacked together in columns and rows with periodic gaps and with discontinuities, the rotating layer alternate and numbers of the rotating layers being equal to numbers of inputs, numbers of columns being equal to numbers of minterms in the standard sum of product (SSoP) formulations, the switches in the same column connected in series and the columns connected in parallel.
Examiner’s Note
9. Applicant is reminded that the Examiner is entitled to give the broadest reasonable interpretation to the language of the claims. Furthermore, the Examiner is not limited to Applicants' definition which is not specifically set forth in the claims. See MPEP 2111, 2123, 2125, 2141.02 VI, and 2182.
Examiner has cited particular paragraphs and/or columns/lines in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner. See MPEP 2141.02 VI.
In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
Conclusion
10. Any inquiry concerning this communication or earlier communications from the examiner should be directed to DIDARUL MAZUMDER whose telephone number is (571)272-8823. The examiner can normally be reached M-F 9-5.
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11. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Partridge can be reached at 571-270-1402. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DIDARUL A MAZUMDER/Primary Examiner, Art Unit 2812
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