DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Preliminary Amendment
Applicant's 3/28/2024 Preliminary Amendment to: 1. Amend the Abstract. 2. Amend the Specification. 3. Amend the Claims is acknowledged by the Office.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 3/28/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: OPTOELECTRONIC COMPONENT WITH CONTROL ELEMENT, OPTOELECTRONIC DEVICE WITH CONTROL ELEMENT, AND METHOD FOR PRODUCING OPTOELECTRONIC COMPONENTS WITH CONTROL ELEMENTS OR OPTOELECTRONIC DEVICES WITH CONTROL ELEMENTS.
Claims Status
Claims 1-17 are currently pending and being examined.
Claim Objections
Claims 5-6, 9 and 15 are objected to because of the following informalities:
A. Grammatical error “the component” in each of claims 5-6 and 9 should read as the optoelectronic component. Appropriate correction is required.
B. Grammatical error “the at least one optoelectronic device” in claim 15 should read as “the at least one optoelectronic component”. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 6 and 15 are rejected under 35 U.S.C. 112(b), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
A. Claim recites the limitation "on the same side" in line 3. There is insufficient antecedent basis for this limitation in the claim.
For examination purposes, "on the same side" in line 3 will be interpreted to read as "on a same side".
B. Claim 15 recites the limitation "the at least one optoelectronic device" in line 2; “at least one of the two electrical contact structures” in lines 2-3; and “the carrier” in lines 3-4. There is insufficient antecedent basis for these limitations in the claim.
For examination purposes, "the at least one optoelectronic device" in line 2; “at least one of the two electrical contact structures” in lines 2-3; and “the carrier” in lines 3-4 will be interpreted to read as "the at least one optoelectronic component"; “at least one of two electrical contact structures”; and “a carrier”, respectively.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 5, 7 and 10-17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Feichtinger et al (US 2011/0188161 A1, hereafter Feichtinger).
Re claim 1, Feichtinger discloses in FIG. 2 an optoelectronic component (structure 1/2; [0044]) comprising
- an optoelectronic semiconductor chip (1; [0044]),
- a control element (varistor 2; [0044]) which is provided for controlling an electric current and/or an electric voltage ([0006]) of the optoelectronic semiconductor chip (1), and comprises a resistive layer (ceramic; [0043]) having a variable electrical resistance (a varistor is by definition a voltage-dependent resistor), wherein the optoelectronic semiconductor chip (1) and the control element (2) are arranged one above the other (stacked) and are mechanically (contact-connected; [0044]) and electrically conductively connected (contact-connected; [0044]) to one another (by 3a; [0044]), and wherein the optoelectronic semiconductor chip (1) and the control element (2) are single (individual) components (separate individual structures),
and
- a first connection electrode (8; [0044]) and a second connection electrode (3b; [0044]) which are provided for electrically contacting ([0044]) the optoelectronic component (1) from the outside ([0044]), wherein the optoelectronic semiconductor chip (1) and the control element (2) are each electrically contacted (in parallel for operation) by one (both) of the first (8) and second (3b) connection electrodes.
Re claim 5, Feichtinger discloses the optoelectronic component according to claim 1, wherein the first connection electrode (8) and the second connection electrode (3b) are arranged at least sectionally (partially) on opposite sides (upper/lower planes) of the optoelectronic component (structure 1/2).
Re claim 7, Feichtinger discloses the optoelectronic component according to claim 1, wherein the control element (varistor 2) comprises a resistive layer (ceramic matrix; [0043]) having a variable electrical resistance (a varistor is by definition a voltage-dependent resistor), and the resistive layer (9) contains an oxide (zinc oxide; [0043]).
Re claim 10, Feichtinger discloses the optoelectronic component according to claim 1, wherein the optoelectronic semiconductor chip (1) and the control element (2) are electrically conductively connected ([0044]) to one another by means of an electrically conductive connecting means (3a; [0044]), wherein the connecting means (3a) contains at least one of the following materials: metal (gold; [0017]), metal compound (gold mixture; [0041]), plastic material, TCO.
Re claim 11, Feichtinger discloses in FIG. 2 an optoelectronic device (structure 1/2/7; [0003] and [0044]) comprising
- at least one optoelectronic component (structure 1/2; [0044]) according to claim 1,
- a carrier (7; [0044]) on which the at least one optoelectronic component (structure 1/2) is arranged,
- a first electrical contact structure (contact wire for connection 8/9; [0044]) to which the first connection electrode (8) of the at least one optoelectronic component (structure 1/2) is electrically conductively connected,
and
- a second electrical contact structure (contact wire for connection 3a/10; [0044]) to which the second connection electrode (3b) of the at least one optoelectronic component (structure 1/2) is electrically conductively connected ([0044]).
Re claim 12, Feichtinger discloses the optoelectronic device according to claim 11, wherein the control element (varistor 2) is arranged on a side (lower plane) of the optoelectronic semiconductor chip (1) of the at least one optoelectronic component (structure 1/2) facing away from (above) the carrier (7).
Re claim 13, Feichtinger discloses the optoelectronic device according to claim 11, wherein the control element (varistor 2) is arranged between the carrier (7) and the optoelectronic semiconductor chip (1) of the at least one optoelectronic component (structure 1/2).
Re claim 14, Feichtinger discloses in FIG. 2 a method for producing at least one optoelectronic component (structure 1/2; [0044]) according to claim 1, comprising the following steps:
- providing at least one control element (see claim 1), which comprises a resistive layer having a variable electrical resistance (see claim 1),
- providing at least one optoelectronic semiconductor chip (see claim 1),
- arranging the at least one control element (varistor 2) on (the lower surface of) the at least one optoelectronic semiconductor chip (1), and connecting (by 3a; see claim 1) the at least one control element (varistor 2) mechanically (see claim 1) and electrically conductively (see claim 1) to the at least one optoelectronic semiconductor chip (1),
- defining at least one first connection electrode (see claim 1) and at least one second connection electrode (see claim 1).
Re claim 15, Feichtinger discloses the method according to the preceding claim, claim 14, wherein for producing the at least one optoelectronic component (structure 1/2) at least one (both) of two electrical contact structures (contact wires for connections 8/9 and 3a/10; [0044]), is produced after arranging the at least one optoelectronic component (structure 1/2) on a carrier (7; [0044]).
Re claim 16, Feichtinger discloses in FIG. 2 a method for producing at least one optoelectronic device (structure 1/2/7; [0003] and [0044]) according to claim 11, comprising the following steps:
- providing at least one control element (see claims 1 and 11), which comprises a resistive layer having a variable electrical resistance (see claims 1 and 11),
- providing at least one optoelectronic semiconductor chip (see claims 1 and 11),
- arranging the at least one control element (varistor 2) on (the lower surface of) the at least one optoelectronic semiconductor chip (1), and connecting (by 3a; see claim 1) the at least one control element (varistor 2) mechanically (see claim 1) and electrically conductively (see claim 1) to the at least one optoelectronic semiconductor chip (1),
- defining at least one first connection electrode (8) and at least one second connection electrode (3b).
Re claim 17, Feichtinger discloses the method according to claim 16, wherein for producing the at least one optoelectronic device (structure 1/2/7) at least one (both) of the two electrical contact structures (contact wires for connections 8/9 and 3a/10) is produced after arranging the at least one optoelectronic component (structure 1/2) on the carrier (7).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Feichtinger in view of HENLEY (US 2018/0374829 A1, hereafter Henly).
Re claim 2, Feichtinger discloses the optoelectronic component according to claim 1.
But, fails to disclose the optoelectronic component (structure 1/2) which has lateral dimensions having values in the single-digit or double-digit micrometer range.
However,
Henley discloses optoelectronic components (micro LEDS; [0002]) which have lateral dimensions having values in the single-digit or double-digit micrometer range (a few microns to 10 µm x 10 µm; [0002] and [0012]).
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the structure of Feichtinger, by using the micro LEDs and their dimensions of Henley for the optoelectronic semiconductor chip of Feichtinger, such that the optoelectronic component (structure 1/2) which has lateral dimensions having values in the single-digit or double-digit micrometer range, for more power efficient and bright display technologies (Henley; [0044]).
Claims 3-4 and 8-9 are rejected under 35 U.S.C. 103 as being unpatentable over Feichtinger in view of Chiozzi (US 2008/0169773 A1).
Re claims 3-4, Feichtinger discloses the optoelectronic component according to claim 1.
But, fails to disclose wherein the control element (varistor 2) does not project laterally beyond the optoelectronic semiconductor chip (1); and wherein the control element (varistor 2) is arranged laterally offset to the optoelectronic semiconductor chip (1).
However,
Chiozzi discloses in FIG. 7 (with references to FIG. 3) an optoelectronic component (structure 1/10) comprising wherein a control element (transistor 10; [0029]; [0037] and [0045]) does not project laterally beyond an optoelectronic semiconductor chip (1; [0045]); and wherein the control element (transistor 10) is arranged laterally offset (different center-lines) to the optoelectronic semiconductor chip (1).
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the structure of Feichtinger, by, firstly, using the transistor of Chiozzi as a control element substitutional equivalent (MPEP § 2144.06) for the varistor of Feichtinger yielding the expected result regulating voltage/current operating the optoelectronic semiconductor chip. And, secondly, rearranging the parts (MPEP § 2144.04 VI. C.) of the optoelectronic component, and its sizes (MPEP § 2144.04 IV. A.), wherein the control element does not project laterally beyond the optoelectronic semiconductor chip; and wherein the control element is arranged laterally offset to the optoelectronic semiconductor chip for side-emitting optoelectronic components.
Re claims 8-9, Feichtinger discloses the optoelectronic component according to claim 1.
But, fails to disclose wherein the control clement (varistor 2) comprises a transistor, which comprises a third connection electrode provided for electrically contacting the optoelectronic component (structure 1/2) from the outside.
However, Chiozzi discloses three-terminal transistors (MOS or bipolar; [0029] and [0037]) which would comprises a third connection electrode provided for electrically contacting the optoelectronic component (structure 1/2) from the outside, as part of the side-emitting optoelectronic components discussed for claims 3-4.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Feichtinger in view of HUANG et al (US 2020/0203582 A1, hereafter Huang).
Re claim 6, Feichtinger discloses the optoelectronic component according to claim 1.
But, fails to disclose wherein the first connection electrode (8) and the second connection electrode (3b) are arranged on a same side of the optoelectronic component (1/2).
However,
Huang discloses in FIGS. 1-2 an optoelectronic component (structure 1/10) comprising wherein a first connection electrode (left 103; [0040]) and a second connection electrode (right 103; [0040]) are arranged on a same side (upper plane of 100) of an optoelectronic component (100/200; [0038]).
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the structure of Feichtinger, by using the ultraviolet or near-ultraviolet LEDs of Huang for the optoelectronic semiconductor chip of Feichtinger, adding the wavelength conversion material layer of Huang, and, lastly, rearranging the parts (MPEP § 2144.04 VI. C.) of the optoelectronic component, such that the first connection electrode and the second connection electrode are arranged on a same side of the optoelectronic component, creating a white light LED package structure (Huang; [0038]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIC W JONES whose telephone number is (408) 918-9765. The examiner can normally be reached M-F 7:00 AM - 6:00 PM PT.
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/ERIC W JONES/Primary Examiner, Art Unit 2892
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