DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 3/28/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Preliminary Amendment
Applicant's 3/28/2024 Preliminary Amendment to: 1. Replace the Abstract. 2. Amend the Specification. 3. Amend the Claims is acknowledged by the Office.
Claims Status
Claims 1-12 are currently pending and being examined.
Claim Objections
Claim 1 is objected to because of the following informalities: the grammatical error “at least one part of the first armature” in line 13 should read as “the at least one part of the first armature”. Appropriate correction is required.
In Re claims 2-12, they are objected to due to their dependence from claim 1.
Claim 6 is objected to because of the following informalities: the grammatical error “The integrated circuit according to claim 1” in line 1 should read as “The integrated circuit according to claim 3”. Appropriate correction is required.
Claim 7 is objected to because of the following informalities: the grammatical error “free of micropost” in line 2 should read as “free of microposts”. Appropriate correction is required.
Claim 8 is objected to because of the following informalities: the grammatical error “Integrated circuit” in line 1 should read as “The integrated circuit”. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 1-12 are rejected under 35 U.S.C. 112(b), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
A. Claim 1 recites the limitation "the transistor" in line 18. There is insufficient antecedent basis for this limitation in the claim. For examination purposes, "the transistor" in line 18 will be interpreted to read as "a transistor".
In Re claims 2-11, they are rejected due to their dependence from claim 1.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-5, 7, 8 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over KIM et al (US 2013/0087887 A1, hereafter Kim) in view of Brewer et al (US 2003/0112576 A1, hereafter Brewer).
Re claim 1, Kim discloses in FIG. 6 An integrated circuit (stack package structure; [0062]) comprising a first chip (120; [0061]) and a second chip (110; [0061]) assembled one on each other (stacked), the first chip (120) being electrically connected to the second chip (110) through a coupling capacitor (130; [0061]) which is located in an inter-chip junction zone (between S1-S3) between the first chip (120) and the second chip (110), the coupling capacitor (130) comprising:
a first conductive armature (134a; [0060]) in electrical contact (through 122; [0063]) with the first chip (120), and
a second conductive armature (132a; [0060]) in electrical contact (through 112; [0063]) with the second chip (110),
at least one part (upper side) of the first armature (134a) being facing the second armature (132a), the first and second armatures (134a/132a) being electrically insulated from each other (by 136; [0062]),
the at least one part of the first armature (upper side) being formed by one or more electrically conductive microposts (134b; [0060]) which each extend from the first chip (120) in the direction of the second chip (110);
in which integrated circuit (stack package structure):
the first armature (134a) of the coupling capacitor (130) is electrically connected to a first electronic component (circuit unit of 120; [0049]) of a data storage ([0049]) or data processing type ([0049]);
the second armature (132a) is electrically connected to a second electronic component (circuit unit of 110; [0049]) of the data storage ([0049]) or data processing type ([0049]).
Kim fails to disclose the first armature (134a) of the coupling capacitor (130) is electrically connected to a first electronic component of a transistor, diode, amplifier, antenna, waveguide or filter type, configured to generate, emit, transmit or filter an electrical signal having a frequency greater than or equal to 10 GHz, or even 300 GHz;
the second armature (132a) is electrically connected to a second electronic component of the transistor, diode, amplifier, antenna, waveguide or filter type.
However,
Brewer discloses in FIG. 1 an integrated circuit comprising: a first electronic component (111; [0027]) of a transistor (Si CMOS), diode, amplifier, antenna, waveguide or filter type, configured to generate, emit, transmit or filter an electrical signal having a frequency greater than or equal to 10 GHz, or even 300 GHz (up to 100 GHz; [0049]); and
a second electronic component (121; [0027]) of the transistor, diode, amplifier, antenna (MICROSTRIP ANTENNA), waveguide or filter type.
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the structure of Kim by adding the first and second electronic components of Brewer to the first and second electronic components, respectively, of Kim, such that the first armature (132a) of the coupling capacitor (130) is electrically connected to a first electronic component (11; 40) of a transistor, diode, amplifier, antenna, waveguide or filter type, configured to generate, emit, transmit or filter an electrical signal having a frequency greater than or equal to 10 GHz, or even 300 GHz; and the second armature (134a) is electrically connected to a second electronic component (21) of the transistor, diode, amplifier, antenna, waveguide or filter type, providing a 3-D structure for high-speed digital and RF applications (Brewer; [0026] and [0049]).
Re claim 2, Kim discloses the integrated circuit according to claim 1, wherein:
each micropost (134b) extends perpendicularly (vertically) to the first chip (120), from the first chip (120) to an end face (top plane) of the micropost (134b),
the second armature (132a) has, for each micropost (134b), a face (bottom plane) or a planar face portion (bottom plane) facing and at a reduced distance (thickness of 136) from the end face (top plane) of this micropost (134b).
Re claim 3, Kim discloses the integrated circuit according to claim 1, wherein at least one part of the second armature (132a) is formed by one or more additional electrically conductive microposts (132b; [0060]), which each extend in the direction of (towards) the first chip (120), from the second chip (110) to an end face (bottom plane) of the additional micropost (132b).
Re claim 4, Kim discloses the integrated circuit according to claim 3, wherein each micropost (134b), as well as each additional micropost (132b), is laterally delimited (defined) by a side surface (left/right vertical sidewalls), and wherein at least some (all) of the additional microposts (132b) are laterally offset (separated) with respect to said microposts (134b), their respective side surfaces (left/right vertical sidewalls) each being facing (opposite) the side surface (left/right vertical sidewalls) of one of said microposts (134b).
Re claim 5, Kim discloses the integrated circuit according to claim 4, wherein at least some (all) of said additional microposts (132b) are sandwiched between microposts (134b) of the first armature (134a).
Re claim 7, Kim discloses the integrated circuit according to claim 2.
But, fails to explicitly disclose wherein the second armature (132a) is free of microposts in the embodiment of FIG. 6. However, Kim discloses in the embodiment of at least FIG. 1 wherein a second armature (132; [0052]) is free of microposts.
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify ([0098]) the structure of Kim by forming the second armature (132a) free of microposts, as a design choice (MPEP § 2144.04), to achieve a desired increase of the capacity of the coupling capacitor ([0060]) from the embodiment of FIG. 1 to the embodiment of FIG. 6.
Re claim 8, Kim discloses the integrated circuit according to claim 1, wherein said microposts (134b) are arranged periodically (alternately with 132b) by forming a regular array (1x4 in cross-section).
Re claim 12, Kim discloses the integrated circuit according to claim 1.
But, fails to disclose wherein the first chip (120) is at least partly formed by a first type of semiconductor material while the second chip (110) is at least partly formed by a second type of semiconductor material different from the first type of semiconductor material.
However, Brewer renders these limitations obvious by disclosing the first electronic component (111) is made of Si/SiGe and the second electronic component (121) is made of GaAs and InP, as would be part of the 3-D structure for high-speed digital and RF applications discussed for claim 1.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Kim and Brewer as applied to claim 1 above, and further in view of Wei et al (US 2009/0002916 A1, hereafter Wei).
Re claim 6, Kim and Brewer disclose the integrated circuit according to claim 3.
But, fail to disclose wherein at least some of the additional microposts (Kim: 132b) each extend facing one of said microposts (134b), the end face (bottom plane) of the additional micropost (132b) considered being facing and at a reduced distance from an end face (top plane) of the corresponding micropost (134b), by being electrically insulated from the end face (top plane) of this micropost (134b).
However,
Wei discloses in FIG. 2 an integrated circuit comprising: wherein at least some of additional microposts (13 of 12; [0017]) each extend facing one of said microposts (13 of 21; [0016]-[0017]), an end face (bottom plane) of the additional micropost (13 of 12) considered being facing and at a reduced distance (separation) from an end face (top plane) of the corresponding micropost (13 of 21), by being electrically insulated (by dielectric materials; [0018]) from the end face (top plane) of this micropost (13 of 21).
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the structure of Kim and Brewer by configuring at least some of the additional microposts (132b) each extend facing one of said microposts (134b), the end face (bottom plane) of the additional micropost considered being facing and at a reduced distance from an end face (top plane) of the corresponding micropost, by being electrically insulated from the end face of this micropost, as disclosed by Wei, modifying the capacitance profile of the integrated circuit to compensate for possible flexure of the integrated circuit (Wei; [0002]).
Claims 9-11 are rejected under 35 U.S.C. 103 as being unpatentable over Kim and Brewer as applied to claim 1 above, and further in view of Miyazawa (US 2003/0183864 A1).
Re claim 9, Kim and Brewer disclose the integrated circuit according to claim 1.
But, fail to disclose wherein at least one part (upper side) of the first armature (Kim: 134a) is separated from the second armature (Kim: 132a) by a distance of less than 2 microns, or even less than 0.5 micron.
However,
Miyazawa discloses in FIG. 1 an integrated circuit comprising: wherein microposts (left/right electrode fingers; [0006]) of first and second armatures (left/right electrodes 12/10) are separated from each other by a distance (finger-to-finger gap; [0006]) of less than 2 microns (about 2 µm; [0006]), or even less than 0.5 micron.
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the structure of Kim and Brewer by configuring the microposts and the additional microposts of first and second armatures to be separated from each other by a distance of less than 2 microns, as disclosed by Miyazawa, such that at least one part (upper side) of the first armature (134a) is separated from the second armature (132a) by a distance of less than 2 microns, for use in a millimeter wave band higher than 30 GHz, and realizing a capacitance as small as tens of fF (Miyazawa; [0006]).
Re claim 10, Kim and Brewer disclose the integrated circuit according to claim 1.
But, fail to disclose wherein the coupling capacitor (130) has an average electric capacitance per unit area greater than or equal to 5 picofarads per square millimetre.
However, Miyazawa discloses the coupling capacitor (interdigital capacitor; [0006]) of FIG. 1 has an average electric capacitance per unit area greater than or equal to 5 picofarads per square millimetre (for a capacitance of 30 fF and an area of 50 µm x 50 µm; [0006]), as would be part of the millimeter wave band capacitor discussed for claim 9.
Re claim 11, Kim and Brewer disclose the integrated circuit according to claim 1.
But, fail to disclose wherein the coupling capacitor (130) has an electric capacitance greater than or equal to 50 femtofarads.
However, Miyazawa discloses in another embodiment (FIG. 5), wherein a coupling capacitor (interdigital capacitor; [0045]) has an electric capacitance greater than or equal to 50 femtofarads (0.05 pF; [0045]).
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the structure of Kim and Brewer by configuring the coupling capacitor of Kim to have an electric capacitance greater than or equal to 50 femtofarads, as disclosed by Miyazawa, as a design choice (MPEP § 2144.04), for use in a millimeter wave band higher than 30 GHz, and realizing a capacitance as small as tens of fF (Miyazawa; [0006]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIC W JONES whose telephone number is (408) 918-9765. The examiner can normally be reached M-F 7:00 AM - 6:00 PM PT.
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/ERIC W JONES/Primary Examiner, Art Unit 2892
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