DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-5, 9-12 and 21 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Sik (KR 2010135100; IDS, 03/28/2024).
Sik is directed to a method of fabricating a photomask. Sik discloses the process comprises forming a phase transition layer (210) and a light-blocking layer (230) on a transparent quartz substrate (100). (Pg.5). Sik discloses different first resist layers (310) and second resist layers (330) are formed on the light-blocking layer (230), where the first resist layer (310) may be formed as a first resist exposed to ultraviolet light, and the second resist layer (330) may be formed as a second resist exposed to an electron beam. (Pg.5). Sik also discloses the first resist can be formed as a negative resist, and the second resist can be formed as a positive resist for electron beam exposure that reacts to an electron beam. (Pg.5). This disclosure teaches the limitation of claim 12. Sik discloses a blank mask is used in which a phase transition layer (210), a light blocking layer (230), and a double layer of resist layers (310, 330) are sequentially stacked on a quartz substrate (100). (Pg. 5; Fig.1). These disclosures and the illustrations of Figure 5 teach the limitations of claim 1, ‘A method of patterning a substrate comprising: providing a first photoresist on the substrate; layering a second photoresist on the first photoresist…’ and the limitation of claims 10-11.
Sik discloses a frame area (101) for frame installation is set on the edge portion of the substrate (100) and a chip area (103) or mask area is set up inside the frame area (101) to which chip patterns to be transferred onto the wafer are located. (Pg.5). Sik discloses, after introducing a blade or mask (400) that exposes the first portion (312) of the second resist layer located in the frame area (101), the first portion (332) of the second resist layer exposed to the mask (400) is selectively exposed for the first time. (Pg.6; Fig.2). Sik discloses this first exposure can be performed as an exposure process using ultraviolet light as an exposure light source. (Pg.6). Sik explains when the second resist layer (330) is composed of a negative resist, the first portion (332) of the second resist layer that was first exposed remains in the subsequent first development process, and the second portion (331) of the second resist layer that was blocked by the mask (400) and was not exposed to the first exposure light source remains. (Pg.6). Sik explains a resist pattern (333) is formed that covers the frame area (101) and exposes the chip area (103). (Pg.6; Fig.3). These disclosures and the illustrations of Figures 2-3 teach the limitations of claim 1, ‘A method of patterning a substrate comprising: … exposing the second photoresist to a first pattern of actinic radiation; developing the second photoresist such that portions of the second photoresist are removed providing gaps between features of the second photoresist, wherein the gaps provide uncovered portions of the first photoresist…’ and the limitation of claims 5 and 21.
Sik discloses next, the lower first resist layer (310) is a resist exposed to an electron beam, and is not exposed by the first exposure, but is partially exposed by the second resist pattern (333). (Pg.6, Fig.4). Sik discloses a second electron beam exposure process is performed to transfer a pattern layout designed on the first resist layer (310) exposed by the second resist pattern (333). (Pg.6). Sik explains the portion of the first resist layer (310) exposed to the second resist pattern (333) is limited to the portion located in the chip area (103). (pg.6). Sik explains pattern transfer is selectively performed only on the portion of the first resist layer (310) exposed by the second electron beam exposure process; therefore, the first portion (311) of the first resist layer exposed to the second electron beam exposure is removed during the subsequent second development process, and the second portion (312) of the first resist layer not exposed to the second electron beam exposure remains. (Pg.6; Fig.5). Sik discloses a first resist layer first pattern (313) is formed and the portion of the first resist layer shielded by the second resist pattern (333) is not exposed to the second electron beam exposure, so it remains as the second pattern (314) of the first resist layer. (Pg.7; Fig.5). These disclosures and illustrations teach the limitation of claim 1, ‘ A method of patterning a substrate comprising: … exposing the first photoresist to a second pattern of actinic radiation; and developing the first photoresist such that portions of the uncovered portions of the first photoresist are removed providing gaps between the features of the first photoresist where a portion of the substrate is exposed.’ These disclosures and illustrations along with the disclosures and illustrations of Sik as discussed above also teach the limitation of claims 2-4 and 9.
Therefore, the recitations of claims 1-5, 9-12 and 21 are anticipated by the disclosures and illustrations of Sik as discussed above.
Claim(s) 1-24 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lai (US 2023/0004087).
Lai discloses a method of manufacturing a semiconductor device. Lai discloses and illustrates a process flow 100 of manufacturing a semiconductor device according to embodiments of the disclosure. (Para, 0026; Fig.1). Lai discloses a layer to be patterned (or a target layer) 20 is formed over a substrate 10. (Para, 0026; Fig.2). Lai discloses one or more layers are formed between the substrate 10 and the target layer 20. (Para, 0026). Lai also explains in one embodiment the target layer 20 is a hardmask layer formed over a substrate 10. (Para, 0044; Fig.8A). Lai discloses the hardmask layer 20 is made of an oxide or nitride, such as a silicon oxide or a silicon nitride or the hardmask layer 20 is a metal or semiconductor layer. (Para, 0044; Fig.8A). These disclosures and illustrations teach the limitation of claims 10-11.
Lai discloses a first resist layer 15a is formed over the surface of a layer to be patterned (or target layer) 20 or, when the target layer 20 not formed, over the surface of the substrate 10, in the first resist coating operation S105. (Para, 0026; Fig.2). Lai discloses the first resist layer 15a undergoes a first baking (or pre-exposure baking) operation to evaporate solvents in the resist composition in the first pre-exposure baking operation S110 in some embodiments. (Para, 0026). Laid discloses a second resist layer 15b is formed over the first resist layer 15a, to form a bi-layer resist 15 in the second resist coating operation S115. (Para, 0026; Fig. 2). These disclosures and illustrations teach the limitation of claim 1, ‘ A method of patterning a substrate comprising: providing a first photoresist on the substrate; layering a second photoresist on the first photoresist…’
Lai discloses in some embodiments the first resist layer 15a includes a chemically-amplified resist (CAR) composition and includes a polymethylmethacrylate (PMMA) or a polyhydroxystyrene (PHS). (Para, 0026). Lai discloses the first resist layer 15a is formed by a spin-coating method. (Para, 0026). Laid discloses in some embodiments, the second resist layer 15b includes a metal-containing photoresist formed by chemical vapor deposition (CVD) or atomic layer deposition (ALD) or is a metal-containing photoresist layer formed by a spin-coating method. (Para, 0026). These disclosures teach the limitation of claims 12, 14-16, 18-19, 22 and 24.
Lai discloses the resist layers 15a, 15b undergo a second baking (or pre-exposure baking) operation S120 to evaporate solvents in the resist composition in some embodiments. The resist layers are baked at a temperature and time sufficient to cure and dry the resist layers. (Para, 0028). Lai explains the resist layers are heated at a temperature of about 40C and 120C for about 10 seconds to about 10 minutes and in some embodiments, each resist layer undergoes pre-exposure baking after each resist layer is formed. (Para, 0028). Lai discloses in other embodiments, the first resist layer 15a and the second resist layer 15b are formed and then both layers are subjected to the pre-exposure baking operation S120. (Para, 0028). These disclosures teach the limitation of claims 17 and 20.
Lai discloses next the second resist layer 15b is selectively exposed to actinic radiation 45. (Para, 0029; Fig.3A-3B). Lai discloses in some embodiments the second resist layer 15b is selectively exposed to ultraviolet radiation which may be deep ultraviolet (DUV) radiation. (Para, 0029). Lai discloses in some embodiments, the ultraviolet radiation is extreme ultraviolet (EUV or XUV) radiation or an electron beam. (Para, 0029). Lai explains the exposure radiation 45 passes through a photomask 30 before irradiating the resist layer 15b, which has a pattern to be replicated in the resist layer 15b. (Para, 0029; Fig. 3A-3B). Lai discloses the pattern is formed by an opaque pattern 35 on photomask substrate 40, which may be formed by a material opaque to ultraviolet radiation, such as chromium, while the photomask substrate 40 is formed of a material that is transparent to ultraviolet radiation, such as fused quartz. (Para, 0030; Fig. 3A-3B). These disclosures and illustrations teach the limitation of claim 1, ‘ A method of patterning a substrate comprising: …exposing the second photoresist to a first pattern of actinic radiation…’ and the limitation of claim 5.
Lai explains, in some embodiments, the selective exposure of the photoresist layer 15a to form exposed regions 50 and unexposed regions 52 is performed using extreme ultraviolet lithography. (Para, 0031). This disclosure and the disclosures of Lai as discussed above teaches the limitation of claims 2-4, 6, 13 and 23. Lai explains a reflective photomask 65 is used to form the patterned exposure light in extreme ultraviolet lithography. (Para, 0031). Lai explains that extreme ultraviolet radiation 95 is directed towards the reflective photomask 65 at an incident angle of about 6°. (Para, 0031). Lai explains a portion 97 of the extreme ultraviolet radiation is reflected by the Si/Mo multilayer 75 towards the photoresist-coated substrate 10, while the portion of the extreme ultraviolet radiation incident upon the absorber layer 85 is absorbed by the photomask. (Para, 0031). Lai explains in some embodiments, additional optics, including mirrors, are between the reflective photomask 65 and the photoresist-coated substrate. (Para, 0031). These disclosures and illustrations teach the limitation of claim 7.
Lai discloses next, the resist layers 15a, 15b undergo a first post exposure bake (PEB) in the first post exposure baking operation S130. (Para, 0035). Lai discloses, in some embodiments, the post-exposure baking causes the reaction product of a first compound or first precursor and a second compound or second precursor in the resist layer 15b that was exposed to actinic energy to further crosslink. (Para, 0035). Lai discloses the selectively exposed resist layer 15b is subsequently developed by applying a developer to the selectively exposed resist layer during the first development operation S135. (Para, 0035; Fig.4). Lai discloses the unexposed portion of the resist layer 52 is removed by the developer 57 forming a pattern of recesses 55 in the resist layer 15b to expose the second resist layer 15a (Para, 0035; Fig.5A). These disclosures and illustrations teach the limitation of claim 1, ‘ A method of patterning a substrate comprising: …developing the second photoresist such that portions of the second photoresist are removed providing gaps between features of the second photoresist, wherein the gaps provide uncovered portions of the first photoresist…’
Lai discloses in some embodiments, a flood exposure is subsequently performed in flood exposure operation S140 which is performed using XUV (EUV) radiation (Para, 0037). Lai explains flood exposure and flood exposing means the XUV radiation is not patterned or selectively scanned prior to impinging on the patterned second photoresist layer 50. (Para, 0037). Lai discloses the XUV (EUV) radiation is not passed through or reflected off a photomask prior to impinging on the patterned second photoresist layer 50. (Para, 0037). Lai discloses in some embodiments, both the patterned second photoresist layer 50 and portions of the first photoresist layer 15a not covered by the patterned second photoresist layer are unmasked to XUV radiation during the flood exposure. (Para, 0037). However, Lai explains, the patterned second photoresist layer 50, masks the underlying first photoresist layer 15a during the flood exposure operation S140 in some embodiments. (Para, 0037). Lai explains in some embodiments, the XUV (EUV) radiation has a wavelength ranging from about 0.1 nm to about 100 nm and in other embodiments, the XUV radiation has a wavelength ranging from about 10 nm to about 30 nm. (Para, 0037). The EUV/XUV radiation source is a laser excited tin plasma in some embodiments and the laser excited tin plasma is filtered in some embodiments to provide a desired exposure wavelength (e.g., 13.5 nm or 50 nm). (Para, 0037). Lai discloses in some embodiments, after the flood exposure, the first resist layer 15a, 15b undergoes a second post exposure baking in second post exposure baking operation S145. (Para, 0038). The time and temperature for the second post exposure baking may be in the same ranges as those disclosed herein for the first post exposure baking operation S130. Lai also discloses that during a second development operation S150 of the first resist layer 15a, any bottom scum is removed along with the exposed areas 15a′ of the first resist layer 15a. (Para, 0039). Lai explains this reduces bottom scum defects, such as bridging and short circuits. (Para, 0039). These disclosures and illustrations as well as the disclosures of Lai discussed above teach the limitation of claim 1, ‘A method of patterning a substrate comprising: …exposing the first photoresist to a second pattern of actinic radiation; and developing the first photoresist such that portions of the uncovered portions of the first photoresist are removed providing gaps between the features of the first photoresist where a portion of the substrate is exposed.’
Lai also discloses in some embodiments, directional exposure techniques are used during the flood exposure operation S140. (Para, 0048). Lai discloses in directional exposure, the incident radiation is directed at an acute angle α relative to a normal line in the z direction intersecting the surface along the x direction of the first photoresist layer. (Para, 0048; Fig.8E). Lai discloses in some embodiments, the acute angle ranges from greater than 0° to about 80°. (Para, 0048). These disclosures teach the limitation of claims 7-8.
Therefore, the recitations of claims 1-24 are anticipated by the disclosures and illustrations of Lai as discussed above.
Conclusion
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/CALEEN O SULLIVAN/Primary Examiner, Art Unit 2899
