Prosecution Insights
Last updated: October 02, 2026
Application No. 18/696,972

COMPONENT WITH A PLURALITY OF SEMICONDUCTOR CHIPS

Non-Final OA §103§112
Filed
Mar 28, 2024
Priority
Sep 28, 2021 — DE 10 2021 125 056.0 +1 more
Examiner
PATEL, REEMA
Art Unit
Tech Center
Assignee
Ams-osram AG
OA Round
1 (Non-Final)
89%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
95%
With Interview

Examiner Intelligence

Grants 89% — above average
89%
Career Allowance Rate
1009 granted / 1136 resolved
+28.8% vs TC avg
Moderate +6% lift
Without
With
+6.4%
Interview Lift
resolved cases with interview
Fast prosecutor
2y 0m
Avg Prosecution
21 currently pending
Career history
1161
Total Applications
across all art units

Statute-Specific Performance

§101
0.5%
-39.5% vs TC avg
§103
43.0%
+3.0% vs TC avg
§102
24.9%
-15.1% vs TC avg
§112
21.4%
-18.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1136 resolved cases

Office Action

§103 §112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Priority Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55. Information Disclosure Statement The information disclosure statement (IDS) was submitted on 3/28/24. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement has been considered by the examiner. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 1 recites the limitation "the common carrier" in lines 10-11. There is insufficient antecedent basis for this limitation in the claim. For the purposes of examination, the examiner interprets “the common carrier” as - - the common metallic carrier - -. However, appropriate correction and/or clarification is requested. Claims 2-20 inherit the 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, rejections based on their dependencies on claim 1. Claim 1 recites the limitation "the housing material" in line 15. There is insufficient antecedent basis for this limitation in the claim. For the purposes of examination, the examiner interprets “the housing material” as - - the electrically insulating housing material - -. However, appropriate correction and/or clarification is requested. Claims 2-20 inherit the 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, rejections based on their dependencies on claim 1. Claim 8 recites the limitation "the housing material" in lines 3 and 7. There is insufficient antecedent basis for this limitation in the claim. For the purposes of examination, the examiner interprets “the housing material” as - - the electrically insulating housing material - -. However, appropriate correction and/or clarification is requested. Claim 9 recites the limitation "the housing material" in lines 3 and 14. There is insufficient antecedent basis for this limitation in the claim. For the purposes of examination, the examiner interprets “the housing material” as - - the electrically insulating housing material - -. However, appropriate correction and/or clarification is requested. Claim 20 recites the limitation "the metallic carrier layer" in line 3. There is insufficient antecedent basis for this limitation in the claim. For the purposes of examination, the examiner interprets “the metallic carrier layer” as - - the common metallic carrier layer - -. However, appropriate correction and/or clarification is requested. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1-2, 4, 6-9, and 19-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Singer et al. (U.S. 2016/0003436 A1; “Singer”) in view of Eichenberg et al. (U.S. 2015/0228630 A1; “Eichenberg”). Regarding claim 1, Singer discloses a component having a plurality of semiconductor chips (10, Fig. 1B) and a carrier (20, Fig. 1B), wherein the carrier (20, Fig. 1B) has a common metallic carrier layer (20, Fig. 1B) with a mounting (top) surface on which the semiconductor chips are arranged, the semiconductor chips are thermally but not electrically conductively connected to the common metallic carrier layer ([0068]-[0069]), the carrier (20, Fig. 1B) has a plurality of contact layers (30, Fig. 1B) which are arranged next to one another and next to the common metallic carrier layer in lateral directions and are configured for electrically contacting the component and thus for electrically contacting the semiconductor chips ([0068]), the carrier (20, Fig. 1B) has an electrically insulating housing material (40, Fig. 1B) which holds the common metallic carrier layer (20, Fig. 1B) and the contact layers (30, Fig. 1B) together, wherein the common metallic carrier layer (20, Fig. 1B) and the contact layers (30, Fig. 1B) are adjacent to the housing material (40, Fig. 1B) and are electrically insulated from each other by the electrically insulating housing material ([0069]), and the semiconductor chips (10, Fig. 1B) are configured to generate electromagnetic radiation during operation of the component ([0001]-[0008]) and comprises at least five semiconductor chips (10, Fig. 1B) in a row and lateral distances between the semiconductor chips is less than 150 µm ([0070]). Yet, Singer does not disclose the semiconductor chips are arranged in at least two rows on the mounting surface. However, Eichenberg discloses semiconductor chips (3, Fig. 1) arranged in at least two rows, containing at least 5 semiconductor chips per row, on a mounting surface ([0054]). This has the advantage of more compactly packing the semiconductor chips of the component. Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to modify the invention of Singer with at least two rows of the semiconductor chips as taught by Eichenberg, so as to more compactly pack the semiconductor chips of the component. Regarding claim 2, Singer discloses the semiconductor chips (10, Fig. 1B) have rear sides, the rear sides facing the common carrier layer and being electrically insulating ([0062]). Regarding claim 4, Singer discloses the semiconductor chips (10, Fig. 1B) are electrically conductively connected to the contact layers (30, Fig. 1B) via bonding wire connections (7, Fig. 1B). Regarding claim 6, Singer discloses the carrier (20, Fig. 1B) has a front side and a rear side facing away from the front side, the front side comprising the mounting surface and the contact layers (30, Fig. 1B) being accessible both on the front side and on the rear side of the carrier. Regarding claim 7, Singer discloses the semiconductor chips (10, Fig. 1B) are controllable in groups or individually via the plurality of contact layers (30, Fig. 1B) ([0068]). Regarding claim 8, Singer discloses a housing body (40, Fig. 1B) which is formed from the electrically insulating housing material (40, Fig. 1B), the component being formed as a QFN component (Quad Flat No-leads), wherein the contact layers (30, Fig. 1B) are at most flush with the housing body (40, Fig. 1B) in lateral directions and do not project laterally beyond the housing body (Fig. 1B-1C). Regarding claim 9, Singer discloses a housing body (40, Fig. 1B) which is formed from the electrically insulating housing material (40, Fig. 1B) and is of frame-like design in plan view (Fig. 1B), wherein the housing body (40, Fig. 1B) has an opening which, in plan view, is framed by side walls of the housing body, the contact layers (30, Fig. 1B) are partially covered by the side walls of the housing body and partially exposed in the opening, and the opening has a bottom surface which is formed sectionally by the mounting surface, sectionally by surfaces of the contact layers and sectionally by surfaces of the housing material. Regarding claim 19, Singer discloses the component is incorporated into a headlight ([0068]-[0069], [0001]). Regarding claim 20, Singer discloses the carrier has two edge-side rows of contact layers (30, Fig. 1C), the metallic carrier layer (20, Fig. 1B) being arranged in a lateral direction between the two rows of contact layers. Claim(s) 3 and 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Singer et al. (U.S. 2016/0003436 A1; “Singer”) as modified by Eichenberg et al. (U.S. 2015/0228630 A1; “Eichenberg”) as applied to claim 1 above, and further in view of Agatani et al. (U.S. 9,018,832 B2; “Agatani”). Regarding claim 3, Singer as modified by Eichenberg discloses the semiconductor chips (Singer: 10, Fig. 1B) are arranged on a mounting surface (Singer: top of 20, Fig. 1B) of a carrier (Singer: 20, Fig. 1B) but does not disclose the mounting surface is provided with an electrically insulating additional layer. However, Agatani discloses a carrier comprising a metal core with a mounting surface provided with an electrically insulating additional layer (col 9, lines 30-33). Because both Singer as modified by Eichenberg and Agatani teach methods of using carriers, it would have been obvious to one skilled in the art at the time the invention was effectively filed to substitute one method for the other to achieve the predictable result of the mounting surface is provided with an electrically insulating additional layer. KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007). Regarding claim 12, Singer as modified by Eichenberg discloses at least two rows of semiconductor chips having at least 5 semiconductor chips per row (see claim 1 rejection above) but does not disclose at least four rows of semiconductor chips. However, Agatani discloses at least four rows of semiconductor chips (11, Fig. 1A). This has the advantage of increasing the lighting capabilities of the component. Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to modify the invention of Singer and Eichenberg with at least four rows of semiconductor chips, as taught by Agatani, so as to increase the lighting capabilities of the component. Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Singer et al. (U.S. 2016/0003436 A1; “Singer”) as modified by Eichenberg et al. (U.S. 2015/0228630 A1; “Eichenberg”) as applied to claim 1 above, and further in view of Lee et al. (U.S. 2008/0087902 A1; “Lee”). Regarding claim 5, Singer as modified by Eichenberg discloses the semiconductor chips (Singer: 10, Fig. 1B) are electrically conductively connected to the contact layers (Singer: 30, Fig. 1B) by bond wires (Singer: 7, Fig. 1B) ([0068]) and not specifically planar electrical connections. However, Lee discloses semiconductor chips electrically connected to contact layers via planar electrical connections (240, Fig. 6-7) ([0068]). Because both Singer as modified by Eichenberg and Lee teach methods of electrically connecting semiconductor elements, it would have been obvious to one skilled in the art at the time the invention was effectively filed to substitute one method for the other to achieve the predictable result of the semiconductor chips electrically conductively connected to the contact layers via planar electrical connections. KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007). Allowable Subject Matter Claims 10-11 and 13-19 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to REEMA PATEL whose telephone number is (571)270-1436. The examiner can normally be reached M-F, 8am-5pm EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine Kim can be reached at (571)272-8458. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /REEMA PATEL/Primary Examiner, Art Unit 2812 9/10/2026
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Prosecution Timeline

Mar 28, 2024
Application Filed
Sep 14, 2026
Non-Final Rejection mailed — §103, §112 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
89%
Grant Probability
95%
With Interview (+6.4%)
2y 0m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1136 resolved cases by this examiner. Grant probability derived from career allowance rate.

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