Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Prior Art of Record
The applicant's attention is directed to additional pertinent prior art cited in the accompanying PTO-892 Notice of References Cited, which, however, may not be currently applied as a basis for the following rejections. While these references were considered during the examination of this application and are deemed relevant to the claimed subject matter, they are not presently being applied as a basis for rejection in this Office action. The pertinence of these documents, however, may be revisited, and they may be applied in subsequent Office actions, particularly in light of any amendments or further clarification of the claimed invention.
Response to Arguments
Applicant’s arguments with respect to claim(s) have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s)1-2, 4-6, 8, 10-12, 18-20- is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yang. (US 2022/0093593 A1).
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CLAIM 1. Yang teaches transistor, comprising: a first electrode 34A and a second electrode 34B arranged on a substrate 10, a semiconductor layer 14A arranged between the first electrode 34A and the second electrode 34B, and a gate electrode GS1 insulated from the semiconductor layer 14A (Yang - Fig. 1; ¶ [0050]-[0053]);
wherein the first electrode 34A and the second electrode 34B are separated in a first direction D1 parallel to the substrate 10 (Yang - Fig. 1; ¶ [0050]-[0053]); the gate electrode GS1 extends along a second direction D2 parallel to the substrate 10 (Yang - Fig. 1; ¶ [0050]-[0053]); the gate electrode GS1 comprises a side wall and two end surfaces, wherein one end surface of the two end surfaces is connected to a word line WL (Yang - Fig. 1; ¶ [0050]-[0053]); at least a portion of the side wall of the gate electrode GS1 and the other end surface of the gate electrode GS1 are surrounded by the semiconductor layer 14A (Yang - Fig. 1; ¶ [0050]-[0053]); and an extension direction D2 of the gate electrode GS1 intersects with an extension direction D3 of the word line WL (Yang - Fig. 1; ¶ [0050]-[0053]).
CLAIM 2. Yang teaches the transistor of claim 1, wherein the first direction D1 intersects with the second direction D2 (Yang - Fig. 1; ¶ [0050]-[0053]); and the word line WL extends along the first direction D1 or a direction D3 perpendicular to the substrate 10 (Yang - Fig. 1; ¶ [0050]-[0053]).
CLAIM 4. Yang teaches the transistor of claim 1, wherein the semiconductor layer 14A surrounding the gate electrode GS1 forms a hollow tubular structure 14A (Yang - Fig. 1; ¶ [0050]-[0053]); the tubular structure 14A has a side surface, a bottom surface and an opening, wherein the side surface comprises two separated electrode contact regions, which are respectively in contact with the first electrode 34A and the second electrode 34B, and a region of the side surface and the bottom surface of the tubular structure located between the first electrode 34A and the second electrode 34B is a channel region 14A (Yang - Fig. 1; ¶ [0050]-[0053]).
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CLAIM 5. Yang teaches the transistor of claim 4, wherein the gate electrode GS1 extends to the bottom surface of the tubular structure 14A through the opening of the tubular structure 14A, and is insulated from the tubular structure 14A through a gate insulation layer 52 (Yang - Fig. 1; ¶ [0050]-[0053]).
CLAIM 6. Yang teaches the transistor of claim 1, wherein the first electrode 34A and the second electrode 34B are located in a same conductive layer parallel to the substrate 10 (Yang - Fig. 1; ¶ [0050]-[0053]); and an outer surface of a channel region of the semiconductor layer 14A is in a same horizontal plane as an outer surface of an adjacent first electrode 34A and/or second electrode 34B (Yang - Fig. 1; ¶ [0050]-[0053]).
CLAIM 8. Yang teaches a 3D stacked semiconductor device 101, comprising a word line WL (Yang - Fig. 1; ¶ [0050]-[0053]); and a plurality of memory cells, distributed in different layers and stacked periodically along a direction D3 perpendicular to a substrate 10 (Yang - Fig. 1; ¶ [0050]-[0053]); wherein each layer comprises a plurality of columns of memory cells, and a memory cell comprises a transistor T1 (Yang - Fig. 1; ¶ [0050]-[0053]); the transistor T1 comprises a first electrode 34A, a second electrode 34B, a semiconductor layer 14A arranged between the first electrode 34A and the second electrode 34B, and a gate electrode GS1 (Yang - Fig. 1; ¶ [0050]-[0053]); the first electrode 34A and the second electrode 34B are separated in a first direction D1 parallel to the substrate 10 (Yang - Fig. 1; ¶ [0050]-[0053]); the gate electrode GS1 extends along a second direction D2 parallel to the substrate 10 (Yang - Fig. 1; ¶ [0050]-[0053]); the gate electrode GS1 comprises a side wall and two end surfaces, one end surface of the two end surfaces is connected to the word line WL (Yang - Fig. 1; ¶ [0050]-[0053]), and at least a portion of the side wall of the gate electrode GS1 and the other end surface of the gate electrode GS1 extending into a hollow annular semiconductor layer 14A are surrounded by the hollow annular semiconductor layer 14A (Yang - Fig. 1; ¶ [0050]-[0053]); and an extension direction D2 of the gate electrode GS1 intersects with an extension direction D3 of the word line WL (Yang - Fig. 1; ¶ [0050]-[0053]).
the transistor comprises a first electrode (e.g. source), a second electrode (e.g. gate), a semiconductor layer (Channel) arranged between the first electrode and the second electrode, and a gate electrode (Fig. 1 & 5);
the first electrode and the second electrode are separated in a first direction parallel to the substrate (Fig. 1 & 5);
the gate electrode comprises a side wall and two end surfaces, one end surface of the two end surfaces is configured to be connected with the word line, and the other end surface of the two end surfaces extends into a hollow annular semiconductor layer (e.g. opening in channel layer); and an extension direction of the gate electrode intersects with an extension direction of the word line (Fig. 1 & 5).
CLAIM 10. Yang teaches the 3D stacked semiconductor device 101 of claim 8, wherein the semiconductor layer 14A surrounding the gate electrode GS1 forms a hollow tubular structure 14A (Yang - Fig. 1; ¶ [0050]-[0053]); the gate electrode GS1 extends to the bottom surface of the tubular structure 14A through the opening of the hollow tubular structure 14A (Yang - Fig. 1; ¶ [0050]-[0053]); the hollow tubular structure 14A has a side surface, a bottom surface and an opening, wherein the side surface comprises two separated electrode contact regions, which are respectively in contact with the first electrode 34A and the second electrode 34B, and a region of the side surface and the bottom surface of the hollow tubular structure 14A located between the first electrode 34A and the second electrode 34B is a channel region 14A (Yang - Fig. 1; ¶ [0050]-[0053]).
CLAIM 11. Yang teaches the 3D stacked semiconductor device 101 of claim 8, wherein the first direction D1 intersects with the second direction D2 (Yang - Fig. 1; ¶ [0050]-[0053]); the word line WL extends along a direction D3 perpendicular to the substrate 10 (Yang - Fig. 1; ¶ [0050]-[0053]); and gate electrodes GS1 of transistors of a column of memory cells located in different layers are connected with a same word line WL (Yang - Fig. 1; ¶ [0050]-[0053]); and the 3D stacked semiconductor device 101 further comprises a plurality of bit lines BL extending along the second direction D2 (Yang - Fig. 1; ¶ [0050]-[0053]); and transistors of a column of memory cells located on a same layer and arranged along the second direction D2 are connected to a same bit line BL (Yang - Fig. 1; ¶ [0050]-[0053]).
CLAIM 12. Yang teaches the 3D stacked semiconductor device 101 of claim 8, wherein the first direction D1 intersects with the second direction D2 (Yang - Fig. 1; ¶ [0050]-[0053]); the word line WL extends along the second direction D2 (Yang - Fig. 1; ¶ [0050]-[0053]); gate electrodes GS1 of transistors of a column of memory cells located in a same layer and arranged along the second direction D2 are connected with a same word line WL (Yang - Fig. 1; ¶ [0050]-[0053]); and the 3D stacked semiconductor device 101 further comprises a plurality of bit lines BL extending along a direction D3 perpendicular to the substrate 10 (Yang - Fig. 1; ¶ [0050]-[0053]); and transistors of a column of memory cells located in different layers are connected to a same bit line BL (Yang - Fig. 1; ¶ [0050]-[0053]).
CLAIM 18. Yang teaches an electronic device, comprising a transistor T1 according to claim 1 (Yang - Fig. 1; ¶ [0050]-[0053]).
CLAIM 19. Yang teaches teaches an electronic device, comprising the 3D semiconductor device 101 according to claim 8 (Yang - Fig. 1; ¶ [0050]-[0053]).
CLAIM 20. Yang teaches the transistor of claim 1, wherein a cross section of the semiconductor layer 14A surrounding the gate electrode GS1 is U-shaped or two separated lines (Yang - Fig. 1; ¶ [0050]-[0053]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yang et al. (US 2022/0093593 A1) in view of Le et al. (US 2018/0366587 A1)
CLAIM 7. Yang teaches the transistor of claim 1 as set forth above (Yang - Fig. 1; ¶ [0050]-[0053]).
Yang does not explicitly disclose that the material of the semiconductor layer 14A is a metal oxide semiconductor material.
Le teaches non-planar and gate-all-around transistor structures (e.g., fins, nanoribbons, nanowires) utilizing an amorphous indium gallium zinc oxide (a-IGZO) material for the semiconductor channel layer 240 to improve electrostatics and reduce leakage (Le - Title; Abstract; Fig. 2C; ¶17-23).
It would have been obvious to a person having ordinary skill in the art (POSITA) at the time of the invention to modify the transistor structure of Yang by substituting the semiconductor channel material 14A with a metal oxide semiconductor material (such as the a-IGZO taught by Le) in order to improve electrostatics and reduce off-state leakage current in the device, since simple substitution of one known element for another to obtain predictable results is considered obvious to one of ordinary skill in the art (KSR International Co. v. Teleflex Inc., 550 U.S.-, 82 USPQ2d 1385).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JARRETT J STARK whose telephone number is (571)272-6005. The examiner can normally be reached 8-4 M-F.
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JARRETT J. STARK
Primary Examiner
Art Unit 2822
10/9/2026
/JARRETT J STARK/Primary Examiner, Art Unit 2898
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