DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, a) a pixel driver circuit 211a and a light emitting device 211b connected to the pixel driver circuit, as well as, the pixel driver circuit of the first sub-pixel unit electrically connected to the first data signal line by a first electrical connection member and a second electrical connection member connected to the second data signal line by a second electrical connection member, recited in claim 1, and b) a first connection terminal electrically connected to the first electrical member … a second connection terminal electrically connect to the second electrical connection member … and a central connection line”, recited in claim 4, must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Moreover, the drawings are objected to as failing to comply with 37 CFR 1.84(p)(4) because reference characters "323" and "T2A" have both been used to designate the same element in Fig. 19. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
The drawings are objected to because in Fig. 4, Psacn1, should read Pscan1. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections
Claim(s) 1-20 is/are objected to because of the following informalities:
With respect to claim 1, “the repeat units” recited in lines 2 and 14 of the claim should read “the plurality of repeat units” and “the first sub-pixel unit” and “the second sub-pixel unit” recited in lines 4, 8 and 10 of the claim, should read “each of the at least one first sub-pixel unit and each of the at least one second sub-pixel unit. Claims 2-19 which either directly or indirectly depend from claim 1 and which inherit issues of claim 1 are objected to for similar reasons.
With respect to claim 2, “the first sub-pixel unit” and “the second sub-pixel unit” recited in lines 2, 5 and 7, should read “the at least one first sub-pixel unit” and “the at least one second sub-pixel unit”. Claims 3-8 which either directly or indirectly depend from claim 2 and which inherit issues of claim 2 are objected to for similar reasons.
With respect to claim 3, “of the second the sub-pixel unit Partially” should read “of the second sub-pixel unit partially”. Moreover, “the first sub-pixel unit” and “the second sub-pixel unit” recited in lines 2-5 of the claim should read “the at least one first sub-pixel unit” and “the at least one second sub-pixel unit”. Claims 4-7 which either directly or indirectly depend from claim 3 and which inherit issues of claim 3 are objected to for similar reasons.
With respect to claim 4, “the first sub-pixel unit” and “the second sub-pixel unit” recited in lines 2 and 4 of the claim should read “the at least one first sub-pixel unit” and “the at least one second sub-pixel unit”
With respect to claim 5, “the repeat units” recited in line 2 and 4 of the claim should read “the plurality of repeat units”. Claims 6-7 which either directly or indirectly depend from claim 1 and which inherit issues of claim 1 are objected to for similar reasons.
With respect to claim 6, “the repeat units” recited in lines 7, 8 and 10 of the claim should read “the plurality of repeat units”. Moreover, “the first sub-pixel unit” and “the second sub-pixel unit” recited in lines 11-12 of the claim should read “the at least one first sub-pixel unit” and “the at least one second sub-pixel unit”. Claim 7 which either directly or indirectly depend from claim 6 and which inherit issues of claim 6 are objected to for similar reasons.
With respect to claim 12, “the driver active portion are” recited in line 12 of the claim should read “the driver active portion is”. Claims 13-19, which either directly or indirectly depend from claim 12 and which inherit issues of claim 12 are objected to for similar reasons.
With respect to claim 13, “are located between the light emitting signal line, the first reset signal line” should read “are located between the light emitting signal line, and the first reset signal line”. Claims 14-19 which either directly or indirectly depend from claim 13 and which inherit issues of claim 13 are objected to for similar reasons.
With respect to claim 14, “the first electrical connection sections” in lines 3-4 of the claim should read “the two first electrical connection sections” and “in adjacent two” recited in line 4 should read “in adjacent ones”.
With respect to claim 20, “the repeat units” recited in lines 3 and 13 should read “the plurality of repeat units” and “the first sub-pixel unit” and ”the second sub-pixel unit” recited in lines 4, 5, 8 and 10 of the claim, should read “the at least one first sub-pixel unit” and “the at least one second sub-pixel unit”.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim(s) 1-20 is/are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
With respect to claim 1, as currently presented the claim recites “a first data signal line and a second data signal line disposed on a side of the repeat units” in lines 1-2 of the claim and “the first data signal line, and the second data signal line are disposed on a same side of the repeat units” in lines 13-14 of the claim. It is unclear if the recited “side” and “same side” are referring to the same side of the repeat units, and what reference frame is being used for defining the claimed side(s) of the repeat units. For purpose of compact prosecution, it will be assumed that the first data signal line, the second data signal line, the first electrical connection member and the second electrical connection member are all located on a same side of the repeat units. Claims 2-19 which either directly or indirectly depend from claim 1 and which inherit issues of claim 1 are rejected for similar reasons.
With respect to claim 3, as currently presented the claim requires that “a pattern of the switch active portion of a first sub-pixel unit is the same as a pattern of the switch active portion of the second sub-pixel unit; wherein the switch active portion of the first sub-pixel unit and the switch active portion of the second the sub-pixel unit Paritally overlap one of the first data signal line and the second data signal line”. It is unclear, however, what is considered a pattern (which suggests a repeating arrangement or sequence of shapes) of the switch active portions of the first and second sub-pixels, and specification provides no guidance on the scope of these terms. Specifically, in paragraphs [0085] and [0134] of the specification as published, it is simply noted that the patterns are the same without any further information of what are considered the claimed patterns or how they are the same? Accordingly, the metes and bounds of the claim are unclear. For purpose of compact prosecution, it will be assumed that a shape of the switch active portions of the switch transistors of the first and second sub-pixel units is the same. Claims 4-7 which either directly or indirectly depend from claim 3 and which inherit issues of claim 3 are rejected for similar reasons.
With respect to claim 4, as currently presented the claim requires that “a central connection line” be disposed between the first connection terminal and the second connection terminal. The meaning of the phrase “central connection line”, however, is unclear and the specification provides no guidance as to the meaning of the phrase. Accordingly, the metes and bounds of the claim are unclear.
With respect to claim 5, as currently presented the claim requires “the first electrical connection member extends near a side of the repeat units, the second electrical connection member extends away from a side of the repeat units”. First, it is unclear if the second and third recited “side” in lines 3-4 were intended to relate back to “a side” (line 2, claim 1), “a same side” (line 13, claim 1) or to set forth an additional side. Second, the term “near” is considered a relative term the scope of which is hard to determined. Namely, it is unclear if the term is simply supposed to indicate that the first electrical connection member extends on a side of the plurality of repeat units or in close proximity to the plurality of repeat units. Third, the scope of the phrase “extends away from a side of the repeat units” is unclear. Namely, it is not clear which direction is considered away from a side. Claims 6-7 which either directly or indirectly depend from claim 5 and which inherit issues of claim 5 are rejected for similar reasons.
With respect to claim 6, as currently presented the claim requires “wherein an interval between the first avoidance section and the repeat units is less than an interval of the first vertical sections between the repeat units, an interval between the second avoidance section and the repeat units is greater than an interval between the second vertical sections and the repeat units”. The scope of the recited term “interval”, however, is unclear. Namely, it is not clear what distance and/or spacing between the recited elements is being considered as being covered by the term “an interval” (e.g. interval between the outside or inside edges of any given element or center of any given element). Claim 7 which directly depends form claim 6 and which inherits issues of claim 6 is rejected for similar reasons.
With respect to claim 8, as currently presented the claim requires “a first electrode of the switch transistor … and a second electrode of the switch transistor … a first electrode of the driver transistor … a second electrode of the driver transistor … a driver gate electrode of the driver transistor … a first electrode of the compensation transistor … a compensation gate electrode of the compensation transistor … a switch gate electrode of the switch transistor”. The antecedent basis for the recited transistors is unclear. Namely, it is not clear to which transistors (e.g. transistors of which of the pixel driver circuit) the recited transistors are referring to. Additionally, it is not clear what covered by the term “a corresponding one of the pixel driver circuits”. Namely, it is not clear what is corresponding to the pixel driver circuits (the first control signal line or the second control signal line or something else). For purpose of compact prosecution, it will be assumed that the recited transistors are referring to one of the set of transistors of the pixel driver circuit of the first sub-pixel or the second sub-pixel.
With respect to claim 9, as currently presented the claim requires that “the pixel driver circuit comprises”. The antecedent basis for the recited “pixel driver”, however, is unclear. Namely, it is not clear to which pixel driver the recited “the pixel driver” is referring to (the pixel driver of the first sub-pixel or the second sub-pixel. For purpose of compact prosecution, it will be assume that “the pixel driver” is referring back to at least the pixel driver of the first sub-pixel of the second sub-pixel. Claims 10 -19 which either directly or indirectly depend from claim 9 and which inherit issues of claim 9 are rejected for similar reasons.
With respect to claim 11, as currently presented the claim requires “a light emitting signal line, a first reset signal line, a third reset signal line, a fourth control signal line” in lines 2-3. It is unclear whether the second recited “a light emitting signal line, a first reset signal line, a third reset signal line, a fourth control signal line” were intended to relate back to “a light emitting signal line, a first reset signal line, a third reset signal line, a fourth control signal line” recited in lines 19, 4, 12, and 10 in claim 9 or to set forth an additional light emitting signal line, first reset signal line, third reset signal line, fourth control signal line. Claims 12-19, which either directly or indirectly depend from claim 11 and which inherit issues of claim 11 and rejected for similar reasons.
With respect to claim 12, the claim recites “the switch transistor” in line 1 and “the driver transistor” in line 3. There is insufficient antecedent basis for these limitations of the claim. For purpose of compact prosecution, “the switch transistor” and “the driver transistor” will be treated as if they were “a switch transistor” and “a driver transistor”. Claims 13-19 which either directly or indirectly depend from claim 12 and which inherit issues of claim 12 are rejected for similar reasons.
With respect to claim 13, the claim recites “the compensation transistor” in line 4. There is insufficient antecedent basis for this limitation of the claim. For purpose of compact prosecution, “the compensation transistor” will be treated as if it were “a compensation transistor”. Claims 14-19 which either directly or indirectly depend from claim 13 and which inherit issues of claim 13 are rejected for similar reasons.
With respect to claim 14, the claim recites “two first electrical connection sections … the first electrical connection section”. It is unclear form the claim language to which one of the two first electrical connection sections introduced in line 2 of the claim the recited “the first electrical connection section” is referring to. Moreover, there is insufficient antecedent basis for the limitation “the sub-pixel units” recited in line 4 of the claim. For purpose of compact prosecution, it will be assumed that “the first electrical connection section” is referring to at least one of the two electrical connection sections.
With respect to claim 18, as currently presented the claim requires that “the first electrical conduction section extend along the second direction and toward a side away from the compensation gate electrode and the second electrical conduction section extend along the second direction and toward a side away from the first reset gate electrode”. The scope of the phrase “toward a side away” is unclear. Specifically, it is not clear which side is considered away from the compensation gate electrode or first reset gate electrode. Claim 19, which directly depends from claim 18 and which inherits issues of claim 18 is rejected for similar reasons.
With respect to claim 19, the claim recites “a second reset signal line” in line 2, “a the fifth control signal line” in line 2, and “a third control signal line” in line 4. To begin with, it is unclear if the claim intended to introduce “a fifth control signal line” or refer back to a fifth control signal line. Moreover, it is unclear whether the second recited “a second reset signal line” and “a third control signal line” were intended to relate back to “a second reset signal line” and “a third control signal line” recited in lines 8 and 6 in claim 9 or to set forth recited “a second reset signal line” and “a third control signal line”.
With respect to claim 20, as currently presented the claim recites “a first data signal line and a second data signal line disposed on a side of the repeat units” in lines 2-3 of the claim and “the first data signal line, and the second data signal line are disposed on a same side of the repeat units” in lines 12-14 of the claim. It is unclear if the recited “side” and “same side” are referring to the same side of the repeat units, and what reference frame is being used for defining the claimed side(s) of the repeat units. For purpose of compact prosecution, it will be assumed that the first data signal line, the second data signal line, the first electrical connection member and the second electrical connection member are all located on a same side of the repeat units.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3 and 20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Shin et al. (US 2023/0217767, hereinafter “Shin”).
Regarding claim 1, Shin teaches in Figs. 1-3 (Fig. 3 shown below) and related text a display panel (110, Fig. 1), comprising a plurality of repeat units (Fig. 3 and ¶[0059]), and a first data signal line (DL4, Fig. 3 and ¶[0064]) and a second data signal line (DL2, Fig. 3 and ¶[0064]) disposed on a side of the repeat units (e.g. on the left side of units R,B, G, Fig. 3),
the (plurality of) repeat units comprising at least one first sub-pixel unit (B, Fig. 3 and ¶[0063]) and at least one second sub-pixel unit (R, Fig. 3 and ¶[0063]), and each of the (at least one) first sub-pixel unit and the (at least one) second sub-pixel unit comprising a pixel driver circuit (RC and BC, Fig. 3 and ¶[0063]) and a light emitting device (RE and BE, Fig. 3 and ¶[0063]) connected to the pixel driver circuit;
wherein the display panel further comprises a first electrical connection member (i.e. a member extending from DL4 to BC, Fig. 3) and a second electrical connection member (i.e. a member extending from DL2 to RC, Fig. 3),
the pixel driver circuit (BC, Fig. 3) of the (at least one) first sub-pixel unit (B, Fig. 3) is electrically connected to the first data signal line (DL4, Fig. 3) by the first electrical connection member, the pixel driver circuit (RC, Fig. 3) of the (at least one) second sub-pixel unit (RC, Fig. 3) is electrically connected to the second data signal line (DL2, Fig. 3) by the second electrical connection member (Fig. 3), and the first electrical connection member, the second electrical connection member, the first data signal line, and the second data signal line are disposed on a same side of the (plurality of) repeat units.
PNG
media_image1.png
621
463
media_image1.png
Greyscale
Regarding claim 2 (1), Shin teaches wherein the pixel driver circuit of each of the (at least one) first sub-pixel unit and the (at least one) second sub-pixel unit comprises a switch transistor (SWT, Fig. 2 and ¶[0043]), a driver transistor (DT, Fig. 2 and ¶[0043]), and a compensation transistor (SET, Fig. 2 and ¶[0043]) connected together, and the switch transistor comprises a switch active portion (i.e. a portion of SWT); and
wherein the switch active portion of the (at least one) first sub-pixel unit is electrically connected to the first data signal line (DL, Figs. 2 and 3) by the first electrical connection member, and the switch active portion of the second sub-pixel unit is electrically connected to the second data signal line by the second electrical connection member (i.e. since the sub-pixel unit is the same for all the sub-pixels the switch active portion of the switch transistor of the at least one second sub-pixel unit would be connected to the second data signal line by the second electrical connection member, Figs. 2-3).
Regarding claim 3 (2), Shin teaches wherein a pattern of the switch active portion of the first sub-pixel unit is the same as a pattern of the switch active portion of the second sub-pixel unit (i.e. since the pixel driver circuit of each of the at least one first sub-pixel unit and the at least one second sub-pixel unit are the same they would have the same pattern (geometric shape), Fig. 2);
wherein the switch active portion of the first sub-pixel unit and the switch active portion of the second the sub-pixel unit partially overlap one of the first data signal line and the second data signal line (i.e. the switch active portion (e.g. portion of SWT connected to DL (DL4), Fig. 2 of the at least one first sub-pixel unit and the switch active portion (e.g. portion of SWT connected to DL (DL2), Fig. 2 of the at least one second sub-pixel unit overlap DL2 and DL4 at least at the point at which they connect to DL2 and DL4, Figs. 2 and 3).
Regarding claim 20, Shin teaches in Figs. 1-3 (Fig. 3 shown above) display device (100, Fig. 1), comprising a display panel (110, Fig. 1), and the display panel comprising a plurality of repeat units (Fig. 3 and ¶[0059]), and a first data signal line DL4, Fig. 3 and ¶[0064]) and a second data signal line (DL2, Fig. 3 and ¶[0064]) disposed on a side (e.g. on the left side of units R, B, G, Fig. 3) of the (plurality of) repeat units,
the (plurality of) repeat units comprising at least one first sub-pixel unit (B, Fig. 3 and ¶[0063]) and at least one second sub-pixel unit (R, Fig. 3 and ¶[0063]), and each of the (at least one) first sub-pixel unit and the (at least one) second sub-pixel unit comprising a pixel driver circuit (RC and BC, Fig. 3 and ¶[0063]) and a light emitting device (RE and BE, Fig. 3 and ¶[0063]) connected to the pixel driver circuit;
wherein the display panel further comprises a first electrical connection member (i.e. a member extending from DL4 to BC, Fig. 3) and a second electrical connection member (i.e. a member extending from DL2 to RC),
the pixel driver circuit (BC, Fig. 3) of the (at least one) first sub-pixel unit (B, Fig. 3) is electrically connected to the first data signal line (DL4, Fig. 3) by the first electrical connection member, the pixel driver circuit (RC, Fig. 3) of the (at least one) second sub-pixel unit (RC, Fig. 3) is electrically connected to the second data signal line (DL2, Fig. 3) by the second electrical connection member (Fig. 3), and the first electrical connection member, the second electrical connection member, the first data signal line, and the second data signal line are disposed on a same side of the (plurality of) repeat units (Fig. 3).
Claim(s) 1-6 and 20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by RA et al. (US 2021/0408209, hereinafter “RA”).
Regarding claim 1, RA teaches in Figs. 1-21 (Fig. 12 shown below) and related text a display panel (Fig. 12), comprising a plurality of repeat units (Fig. 12 and ¶[0060]), and a first data signal line (171a (DL1), Fig. 12 and ¶[0077]) and a second data signal line (171b (DL2), Fig. 12 and ¶[0077]) disposed on a side of the repeat units (Fig. 12),
the (plurality of) repeat units comprising at least one first sub-pixel unit (PX1, Fig. 12 and ¶[0060]) and at least one second sub-pixel unit (PX2, Fig. 12 and ¶[0060]), and each of the (at least one) first sub-pixel unit and the (at least one) second sub-pixel unit comprising a pixel driver circuit (T1-T3, Fig. 12 and ¶[0060]) and a light emitting device (ED, Fig. 12 and ¶[0060]) connected to the pixel driver circuit;
wherein the display panel further comprises a first electrical connection member (e.g. 178 connected to PX1, Fig. 12 and ¶[0113]) and a second electrical connection member (e.g. 178 connected to PX3, Fig. 12),
the pixel driver circuit (T1-T2, Fig. 12) of the (at least one) first sub-pixel unit (e.g. PX1, Fig. 12) is electrically connected to the first data signal line (171a (DL1), Fig. 12) by the first electrical connection member (178, Fig. 12), the pixel driver circuit (T1-T3, Fig. 12) of the (at least one) second sub-pixel unit (e.g. PIX3, Fig. 12) is electrically connected to the second data signal line (171b (DL2), Fig. 12) by the second electrical connection member (178, Fig. 12), and the first electrical connection member, the second electrical connection member, the first data signal line, and the second data signal line are disposed on a same side of the (plurality of) repeat units (Fig. 12).
PNG
media_image2.png
567
541
media_image2.png
Greyscale
Regarding claim 2 (1), RA teaches wherein the pixel driver circuit of each of the (at least one) first sub-pixel unit and the (at least one) second sub-pixel unit comprises a switch transistor (T2, Figs. 11, 12 and ¶[0063]), a driver transistor (T1, Figs. 11, 12 and ¶[0062]), and a compensation transistor (T3, Figs. 11, 12 and ¶[0063]) connected together, and the switch transistor comprises a switch active portion (i.e. a portion of T2, Fig. 12); and
wherein the switch active portion of the (at least one) first sub-pixel unit is electrically connected to the first data signal line (171a (DL1), Figs. 11 and 12) by the first electrical connection member (178, Fig. 12), and the switch active portion of the second sub-pixel unit is electrically connected to the second data signal line (171b (DL2), Figs. 11-12) by the second electrical connection member (178, Fig. 12).
Regarding claim 3 (2), RA wherein a pattern (i.e. shape) of the switch active portion of the first sub-pixel unit is the same as a pattern of the switch active portion of the second sub-pixel unit (i.e. the shape of T2 transistors of each pixel is the same, Figs. 7 and 12);
wherein the switch active portion of the first sub-pixel unit and the switch active portion of the second the sub-pixel unit partially overlap one of the first data signal line and the second data signal line (171a (DL1), 171b (DL2), Fig. 12).
Regarding claim 4 (3), RA teaches wherein the switch active portion of the first sub-pixel unit (i.e. switch active portion of T2 of PX1, Figs. 12 and 13) comprises a first connection terminal (162 of PX1, Figs. 12 and 13) electrically connected to the first electrical connection member (178 of PX1, Figs. 12 and 13), and the switch active portion of the second sub-pixel unit (i.e. switch active portion of T2 of PX3, Figs. 12 and 13) comprises a second connection terminal (162 of PX3, Figs. 12 and 13) electrically connected to the second electrical connection member (178 of PX3, Figs. 12 and 13);
wherein the first connection terminal (162, Fig. 13) and the second connection terminal (162, Fig. 13) are disposed between the first data signal line (171a, Fig. 13) and the second data signal line (i.e. 171b of PIX3 would be disposed in the same manner as 171a of PIX1 shown in Fig. 13), and a central connection line between the first connection terminal and the second connection terminal is parallel to a second direction (Figs. 12 and 13).
Regarding claim 5 (3), RA teaches wherein the first data signal line (171a (DL1), Figs. 11 and 12) is disposed between the repeat units and the second data signal line (171b (DL2), Figs. 11 and 12);
wherein the first electrical connection member (178 of PX1, Fig. 12) extends near a side of the repeat units, the second electrical connection member (178 of PX3, Fig. 12) extends away from a side of the repeat units, the first electrical connection member (178 of PX1, Fig. 12) partially overlaps the first data signal line (171a (DL1) of PX1, Fig. 12), the first electrical connection member does not overlap the second data signal line (Fig. 12), the second electrical connection member (178 of PX3, Fig. 12) partially overlaps the second data signal line (171b (DL2) of PX1, Fig. 12), and the second electrical connection member does not overlap the first data signal line (171a (DL1), Fig. 12).
Regarding claim 6 (5), RA teaches wherein the first data signal line (171a (DL1), Fig. 12) comprises a plurality of first vertical sections (i.e. two straight end sections of 171a extending along D1 direction, Figs. 12 and 15) and a first avoidance section (i.e. section of 171a between two straight end sections of 171a, Figs. 12 and 15) disposed between adjacent two of the first vertical sections (Figs. 12 and 15), the second data signal line comprises a plurality of second vertical sections (i.e. two straight end sections of 171b extending along D1 direction, Figs. 12 and 15) and a second avoidance section (i.e. section of 171b extending between two straight end sections of 171b, Figs. 12 and 15) disposed between adjacent two of the second vertical sections, and the first avoidance section is opposite and parallel to the second avoidance section (Figs. 12 and 15);
wherein an interval between the first avoidance section and the repeat units is less than an interval of the first vertical sections between the repeat units (Figs. 12 and 15), an interval between the second avoidance section and the repeat units is greater than an interval between the second vertical sections and the repeat units (Figs. 12 and 15),
the switch active portion of the first sub-pixel unit (i.e. portion of T2 transistor of PX1, Fig. 12) is electrically connected to the first avoidance section by the first electrical connection member (178, Fig. 12), and the switch active portion of the second sub-pixel unit (i.e. portion of T2 transistor of PX3, Fig. 12) is electrically connected to the second avoidance section by the second electrical connection member (178 of PX3, Fig. 12).
Regarding claim 20, RA teaches in Figs. 1-21 (Fig. 12 shown above) and related text a display device (Fig. 12), comprising a display panel (Fig. 12), and the display panel comprising a plurality of repeat units (Fig. 12 and ¶[0060]), and a first data signal line (171a (DL1), Fig. 12 and ¶[0077]) and a second data signal line (171b (DL2), Fig. 12 and ¶[0077]) disposed on a side of the repeat units (Fig. 12),
the (plurality of) repeat units comprising at least one first sub-pixel unit (PX1, Fig. 12 and ¶[0060]) and at least one second sub-pixel unit (PX2, Fig. 12 and ¶[0060]), and each of the (at least one) first sub-pixel unit and the (at least one) second sub-pixel unit comprising a pixel driver circuit (T1-T3, Fig. 12 and ¶[0060]) and a light emitting device (ED, Fig. 12 and ¶[0060]) connected to the pixel driver circuit;
wherein the display panel further comprises a first electrical connection member (e.g. 178 connected to PX1, Fig. 12 and ¶[0113]) and a second electrical connection member (e.g. 178 connected to PX3, Fig. 12),
the pixel driver circuit (T1-T2, Fig. 12) of the (at least one) first sub-pixel unit (e.g. PX1, Fig. 12) is electrically connected to the first data signal line (171a (DL1), Fig. 12) by the first electrical connection member (178, Fig. 12), the pixel driver circuit (T1-T3, Fig. 12) of the (at least one) second sub-pixel unit (e.g. PIX3, Fig. 12) is electrically connected to the second data signal line (171b (DL2), Fig. 12) by the second electrical connection member (178, Fig. 12), and the first electrical connection member, the second electrical connection member, the first data signal line, and the second data signal line are disposed on a same side of the (plurality of) repeat units (Fig. 12).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 9-10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shin as applied to claims 2 and 1 above, respectively, and further in view of Wang (CN 117456891, hereinafter “Wang `891”).
Regarding claim 9 (1), teaching of Shin was discussed above in the rejection of claim 1 and includes the pixel driver circuit. Shin, however, does not explicitly teach that the pixel driver circuit further comprises a first reset transistor, wherein a first electrode of the first reset transistor is connected to a first reset signal line, a second electrode of the first reset transistor is connected to a third node, and a first reset gate electrode of the first reset transistor is connected to a third control signal line; a second reset transistor, wherein a first electrode of the second reset transistor is connected to a second reset signal line, a second electrode of the second reset transistor is connected to an anode of the light emitting device, and a second reset gate electrode of the second reset transistor is connected to a fourth control signal line; a third reset transistor, wherein a first electrode of the third reset transistor is connected to a third reset signal line, a second electrode of the third reset transistor is connected to a first node, and a third reset gate electrode of the third reset transistor is connected to the fourth control signal line; a first light emitting transistor, wherein a first electrode of the first light emitting transistor is connected to a first high electrical potential line, a second electrode of the first light emitting transistor is connected to the first node, and a first light emitting gate electrode of the first light emitting transistor is connected to a light emitting signal line; a second light emitting transistor, wherein a first electrode of the second light emitting transistor is connected to a second node, a second electrode of the second light emitting transistor is connected to an anode of the light emitting device, and a second light emitting gate electrode of the second light emitting transistor is connected to the light emitting signal line; a storage capacitor, wherein the storage capacitor comprises a first electrode plate and a second electrode plate, the first electrode plate is connected to the third node, and the second electrode plate is connected to the first high electrical potential line; a boost capacitor, wherein the boost capacitor comprises a third electrode plate and a fourth electrode plate, the third electrode plate is connected to the third node, and the fourth electrode plate is connected to a second control signal line.
Wang `891, in a similar field of endeavor, teaches in Fig. 1 (shown above) and related text, a pixel driver circuit (Fig. 1) for driving a light emitting device of a display panel similar to that disclosed by Shin, that comprises:
a first reset transistor (T4, Fig. 1), wherein a first electrode of the first reset transistor is connected to a first reset signal line (Vi1, Fig. 1), a second electrode of the first reset transistor is connected to a third node (Q, Fig. 1), and a first reset gate electrode of the first reset transistor is connected to a third control signal line (Nscan2, Fig. 1);
a second reset transistor (T7, Fig. 1), wherein a first electrode of the second reset transistor is connected to a second reset signal line (Vi2, Fig. 1), a second electrode of the second reset transistor is connected to an anode of the light emitting device (Fig. 1), and a second reset gate electrode of the second reset transistor is connected to a fourth control signal line (Pscan2, Fig. 1);
a third reset transistor (T8, Fig. 1), wherein a first electrode of the third reset transistor is connected to a third reset signal line (Vi3, Fig. 1), a second electrode of the third reset transistor is connected to a first node (A, Fig. 1), and a third reset gate electrode of the third reset transistor is connected to the fourth control signal line (Pscan2, Fig. 1);
a first light emitting transistor (T5, Fig. 1), wherein a first electrode of the first light emitting transistor is connected to a first high electrical potential line (VDD, Fig. 1), a second electrode of the first light emitting transistor is connected to the first node (A, Fig. 1), and a first light emitting gate electrode of the first light emitting transistor is connected to a light emitting signal line (EM, Fig. 1);
a second light emitting transistor (T6, Fig. 1), wherein a first electrode of the second light emitting transistor is connected to a second node (C, Fig. 1), a second electrode of the second light emitting transistor is connected to an anode of the light emitting device (Fig. 1), and a second light emitting gate electrode of the second light emitting transistor is connected to the light emitting signal line (EM, Fig. 1);
a storage capacitor (Cst, Fig. 1), wherein the storage capacitor comprises a first electrode plate (Fig. 1) and a second electrode plate (Fig. 1), the first electrode plate is connected to the third node (Q, Fig. 1), and the second electrode plate is connected to the first high electrical potential line (VDD, Fig. 1);
a boost capacitor (Cboost, Fig. 1), wherein the boost capacitor comprises a third electrode plate (Fig. 1) and a fourth electrode plate (Fig. 1), the third electrode plate is connected to the third node (Fig. 1), and the fourth electrode plate is connected to a second control signal line (Pscan, Fig. 1) in order to improve quality of the display panel.
PNG
media_image3.png
610
551
media_image3.png
Greyscale
Thus, since the prior art teaches all of the claim elements, using such elements would lead to predictable results, and as such, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to used to pixel driver circuit disclosed by Wang `891 in the display panel disclosed by Shin, in order to improve quality of the display panel.
Regarding claim 10 (9), the combined teaching of Shin and Wang `891 was discussed above in the rejection of claim 9, While Shin and Wang do not explicitly teach that a capacitor value of the boost capacitor is less than a capacitor value of the storage capacitor, selecting different values for the boost and storage capacitors disclosed by Shin and Wang `891 would have been within the capabilities of one of ordinary skill in the art in order to meet specific design requirements for the pixel driver circuit. Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to select the value of the boost capacitor disclosed by Shing and Wang, so that is less than the value of the storage capacitor in order to meet specific design requirements for the pixel driver circuit.
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shin and Wang `891 as applied to claim 9 above, and further in view of Wang et al (US 2024/0233635, hereinafter “Wang `635”).
Regarding claim 11 (9), the combined teaching of Shin and Wang `891 was discussed above in the rejection of claim 9 and includes a light emitting signal line (EM, Fig. 1), a first reset signal line (Vi1, Fig. 1), a third reset signal line (Vi3, Fig. 1), and a fourth control signal line (Pscan2, Fig. 1). While Shin and Wang `891 do not explicitly teach that a first gate electrode layer of the display panel comprises the light emitting signal line, the first reset signal line, the third reset signal line, the fourth control signal line, wherein each of the light emitting signal line, the first reset signal line, the third reset signal line, and the fourth control signal line extends along a first direction, and the third reset signal line, the fourth control signal line, the light emitting signal line, and the first reset signal line are arranged at intervals along a second direction, including the light emitting signal line, the first reset signal line, the third reset signal line and the fourth control line as part of a first gate electrode layer would have been obvious to one of ordinary skill in the art as evidenced by Wang `635, who in a similar field of endeavor explicitly teaches in Fig. 5 and related text that light emitting signal line (EML, Fig. 5), the first reset signal line (RL1, Fig. 5), the third reset signal line (RL2) and the fourth control line (GL1, Fig. 5) can be formed as part of the first gate control layer in order to meet specific circuit layout design requirements for the pixel driver circuit.
Thus, since the prior art teaches all of the claim elements, using such elements would lead to predictable results and, as such, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the light emitting signal line, the first reset signal line, the third reset signal line and the fourth control line, disclosed by Shin and Wang `891 as part of a first gate electrode layer, as disclosed by Wang `635, such that each of the light emitting signal line, the first reset signal line, the third reset signal line, and the fourth control signal line disclosed extends along a first direction, and the third reset signal line, the fourth control signal line, the light emitting signal line, and the first reset signal line are arranged at intervals along a second direction in order to meet specific circuit layout design requirements for the pixel driver circuit.
Relevant Prior Art
The following prior art is relevant to the invention but not relied upon in any of the rejections:
Jeon et al. (US 2022/0199742) discloses in Figs. 1-38 and related text, a display panel that includes a plurality of repeat units with first and second data signal lines disposed on one side of the plurality of repeat units, where each of the at least first and second sub-pixel units comprise a pixel driver circuit and a light emitting device connected to the pixel driver circuit, wherein the display panel further comprises a first electrical connection member and a second electrical connection member the pixel driver circuit of the (at least one) first sub-pixel unit is electrically connected to the first data signal line by the first electrical connection member (, the pixel driver circuit of the (at least one) second sub-pixel unit is electrically connected to the second data signal line by the second electrical connection member and the first electrical connection member, the second electrical connection member, the first data signal line, and the second data signal line are disposed on a same side of the (plurality of) repeat units.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANETA B CIESLEWICZ whose telephone number is 303-297-4232. The examiner can normally be reached M-F 8:30 AM - 2:30 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sue Purvis can be reached at 571-272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/A.B.C/Examiner, Art Unit 2893
/SUE A PURVIS/Supervisory Patent Examiner, Art Unit 2893
Prosecution Insights