Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 3/2/2026 have been fully considered but they are not persuasive.
Regarding claim 1, Applicant alleges that Ueda does not disclose the limitation: “wherein, in the second direction, a width of the first wiring portion and a width of the second wiring portion are each 1.1 times to 4.0 times an average value of widths of the plurality of third wiring portions” as recited in claim 1.
Applicant’s arguments regarding this limitation have been fully considered but are not persuasive.
In the Office action dated 12/4/2025, this limitation was reasonably construed as each width of the first and second wiring portions are added together (“a width of the first wiring portion and a width of the second wiring portion,” emphasis added), and the sum of the two widths is 1.1 to 4 times the average value of widths of the inner portions. This limitation is anticipated by Ueda, Figs. 1-2 and [0032], [0036], [0041]-0043] as clarified in the Office action.
However, in Applicant’s arguments filed on 3/2/2026, Applicant, on pages 7-9, establishes and enters into the record that this limitation shall be more narrowly construed such that a width of the first wiring portion is 1.1 times to 4.0 times the average widths of the inner portions, and also a width of the second wiring portion is 1.1 times to 4.0 times the average widths of the inner portions. Applicant points to Fig. 3 of Applicant’s specification, annotated below, where the respective individual widths of the two outer wiring portions are 1.1 times to 4.0 times the average widths of the inner portions.
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Applicant alleges that claim 1 is allowable over Ueda under 102 under this narrower claim construction.
The Examiner respectfully disagrees with Applicant’s allegation because Ueda, Fig. 7 and [0075]-[0076] also anticipates the narrower construction of this limitation. Ueda discloses that each of the outer wiring portions 31 has a width of 30 μm and each of the inner wiring portions 30 has a width of 20 μm. Therefore, Ueda reads on the narrower construction of the limitation: “wherein, in the second direction, a width of the first wiring portion and a width of the second wiring portion are each 1.1 times to 4.0 times an average value of widths of the plurality of third wiring portions” as recited in claim 1. See Ueda, Fig. 7, annotated below.
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The Examiner respectfully submits that Ueda anticipates the narrower construction of claim 1. Therefore, Applicant’s arguments that claim 1 is allowable under 102 over Ueda are not persuasive.
Claim 7, which depends from claim 1, is hereby rejected under a new grounds in view of the narrower construction of claim 1. As such, Applicant’s arguments regarding claim 7 are moot.
Regarding claim 2, on pages 14-15, Applicant notes that the seed layer 2 of Ueda “is formed on almost the entire surface of the base film 1 by electroless plating.” (Ueda, Fig. 3, [0054]). Applicant alleges that because Ueda already includes a seed layer applied to the base layer, there is no need to modify Ueda’s board to incorporate Hong’s second seed layer. Applicant further alleges that there is no teaching or suggestion in Ueda or Hong that Ueda’s circuit board would benefit from Hong’s second seed layer. Therefore, Applicant alleges that claim 2 is allowable under 103 over Ueda in view of Hong.
Applicant’s arguments regarding this limitation have been fully considered but are not persuasive.
The Examiner respectfully notes that Ueda, [0054], teaches that the seed layer 2 “is formed on almost the entire surface of the base film 1 by electroless plating.” (Emphasis added). The Examiner respectfully submits that a person having ordinary skill in the art would understand that Ueda [0054] teaches that the seed layer 2 is not formed on the entire surface of the base film 1.
Hong, [0079] teaches the second seed layer covers the first seed layer and also the portions of the substrate that are not covered by the first seed layer. The metal layer is disposed on the second seed layer. A person having ordinary skill in the art would have reasonably recognized that Hong’s second seed layer could be applied to Ueda’s seed layer so that the entire surface of the base film 1 can be covered with a seed layer. Therefore, non-formation part of the metal layer does not occur and there is no problem that performance of the coil component is deteriorated, as suggested by Hong at [0079].
Furthermore, it is noted that the combination of Hong’s second seed layer with Ueda’s circuit board does not destroy the principle operation of Ueda.
For the reasons discussed above, the Examiner respectfully submits that Applicant’s arguments with respect to claim 2 are not persuasive.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim 1 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by “Ueda” (US 2022/0167498).
Regarding claim 1, Ueda anticipates 1. A printed circuit board comprising: a base film having a main surface; and an electrically conductive pattern disposed on the main surface (Figs. 1, 2, 7, [0032], [0036], [0041]-[0043], [0075]-[0076]; the printed circuit board 50 comprises a base film 1 has a main surface, and a seed layer 2 is disposed on the main surface of the base film 1),
wherein a normal line of the main surface is along a first direction, wherein the electrically conductive pattern includes a plurality of wiring portions disposed side by side along a second direction to be spaced apart from each other, the second direction being orthogonal to the first direction (Figs. 1, 2, 7, [0032], [0036], [0041]-[0043], [0075]-[0076]; a normal line of the main surface is a first direction, and the conductive pattern 20 includes the outermost boundary wiring portion 31 and the inner wiring portions 30 disposed side by side in an orthogonal direction to the first direction, see Fig. 7),
wherein the plurality of wiring portions include a first wiring portion and a second wiring portion that are each present at a corresponding one of both ends in the second direction and a plurality of third wiring portions that are present between the first wiring portion and the second wiring portion in the second direction, and wherein, in the second direction, a width of the first wiring portion and a width of the second wiring portion are each 1.1 times to 4.0 times an average value of widths of the plurality of third wiring portions (Figs. 1, 2, 7, [0032], [0036], [0041]-[0043], [0075]-[0076]; the wiring portion 31 on the left is a first wiring portion, the wiring portion 31 on the right is a second wiring portion, and the and the inner wiring portions 30 in between the first and second wiring portions are third wiring portions, the width of the individual wiring portions 31 is 30 μm and the width of the third wiring portions 10 is 20 μm, thus the aspect ratio is 1.5, see Fig. 7).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 2-4 and 6 are rejected under 35 U.S.C. 103 as being unpatentable over Ueda in view of “Hong” (US 2017/0133145).
Regarding claim 2, Ueda discloses the claimed invention as applied to claim 1, above.
Ueda discloses 2. The printed circuit board according to claim 1, wherein the electrically conductive pattern includes a seed layer disposed on the main surface (Figs. 1, 2, [0036]; the seed layer 2 is disposed on the main surface),
and an electroplating layer disposed on the seed layer (Figs. 1, 2, [0038]; the metal layer 3 is formed by electroplating and is disposed on the seed layer 2),
and wherein the electroplating layer is made of copper (Figs. 1, 2, [0038]; the metal layer 3 is formed by electroplating and is made of copper).
Ueda does not disclose an electroless plating layer disposed on the seed layer, an electroplating layer disposed on the electroless plating layer, wherein the electroless plating layer is made of copper.
Hong discloses an electroless plating layer disposed on the seed layer, an electroplating layer disposed on the electroless plating layer, wherein the electroless plating layer is made of copper (Fig. 4C, [0104] the seed layer 22 is formed of copper, the second seed layer 23 is an electroless plating layer formed of copper, and the metal layer 24 is formed of copper and is disposed on the second seed layer 23 by electroplating).
It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to have constructed Ueda’s conductive pattern with Hong’s pattern in order to provide a coil component having excellent productivity, having a small coil loss factor, and improving resolution of a fine line width, and a method capable of efficiently manufacturing the same, as suggested by Hong at [0003]. Furthermore, it would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, that Hong’s second seed layer could be applied to Ueda’s seed layer, which does not cover Ueda’s entire substrate, so that the non-formation part of the metal layer does not occur and there is no problem that performance of the coil component is deteriorated, as suggested by Hong at [0079].
Regarding claim 3, Ueda in view of Hong discloses the claimed invention as applied to claim 2, above.
Ueda discloses 3. The printed circuit board according to claim 2, wherein the width of the first wiring portion and the width of the second wiring portion are each 5 μm to 60 μm (Figs. 1, 2, [0032], [0036], [0041]-[0043]; the innermost inner wiring portion 10 is a first wiring portion having a width of20 μm , the outermost boundary wiring portion 11 is a second wiring portion having a width of 30 μm).
Regarding claim 4, Ueda in view of Hong discloses the claimed invention as applied to claim 2, above.
Ueda discloses 4. The printed circuit board according to claim 2, wherein a thickness of the electrically conductive pattern is 5 μm to 150 μm (Figs. 1, 2, [0034], [0036], [0039]; the thickness of the base film 1 is preferably 5 μm, the thickness of the seed layer 2 is 10 nm or more and 2 μm or less, the thickness of the metal layer 3 is 1 μm or more and 10 μm or less, therefore the thickness of the electrically conductive pattern 20 is 5 μm to 150 μm).
Regarding claim 6, Ueda in view of Hong discloses the claimed invention as applied to claim 2, above.
Ueda discloses 6. The printed circuit board according to claim 2, wherein a distance between two of the plurality of wiring portions, the two being adjacent to each other in the second direction, is 20 μm or less (Figs. 1, 2, [0046]; the average interval D of the plurality of inner wiring portions 10 is preferably 2 μm and is more preferably 5 μm).
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Ueda in view of “Sakai” (US 2021/0153358).
Regarding claim 5, Ueda in view of Hong discloses the claimed invention as applied to claim 2, above.
Ueda does not disclose the limitations of claim 5.
Sakai discloses 5. The printed circuit board according to claim 2, wherein a void density at an interface between the electroless plating layer and the electroplating layer is 5.5 μm2/μm or less (Abstract, A void density at an interface between the electroless plating layer and the electroplating layer in a section of the plurality of wiring parts in a thickness direction is 0.01 μm2/μm or less).
It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to have constructed Ueda’s conductive pattern with Sakai’s pattern in order to provide for a printed circuit board that is capable of sufficiently suppressing separation between an electroless plating layer and an electroplating layer of wiring parts even when the width of each of the wiring parts is reduced, as suggested by Sakai at [0019].
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Ueda.
Regarding claim 7, Ueda discloses the claimed invention as applied to claim 1, above.
The embodiment of Ueda, Fig. 7, as relied on in the 102 rejection of claim 1, does not disclose the electrically conductive pattern is wound into a spiral shape in plan view and forms a coil.
In a different embodiment, Ueda discloses wherein the electrically conductive pattern is wound into a spiral shape in plan view and forms a coil (Figs. 1, 2, [0032], [0036], [0041]-[0043], [0075]; the conductive pattern 20 is wound into a spiral shape in plan view and forms a coil),
wherein the first wiring portion is present at an innermost periphery of the coil (Figs. 1, 2, [0032], [0036], [0041]-[0043], [0075]; the innermost inner wiring portion 10 is a first wiring portion),
and wherein the second wiring portion is present at an outermost periphery of the coil (Figs. 1, 2, [0032], [0036], [0041]-[0043], [0075]; the outermost boundary wiring portion 11 is a second wiring portion).
It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to have constructed Ueda’s conductive pattern of Fig. 7 into a spiral shape in plan view and forms a coil since Ueda does not limit the conductive pattern to linear shapes. Ueda also teaches that the conductive pattern can be a spiral shape at [0075]. Furthermore, Ueda, [0076] discloses the benefits of the larger widths of the two outermost boundaries so that peeling can be suppressed.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to STANLEY TSO whose telephone number is (571)270-0723. The examiner can normally be reached Tu-Thurs 6am-6pm, alt M 6am-2pm.
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/STANLEY TSO/Primary Examiner, Art Unit 2847