DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
2. Claims 1-17 are presented for examination.
Claim Interpretation
3. Examiner acknowledged the applicant’s arguments on page 10 of the applicant’s remark regarding to 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, 6th paragraph. The Examiner will proceed with this examination as the claims do not invoke 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, 6th paragraph in view of applicant's amendments/remarks.
Claim Rejections - 35 U$C § 101
4. The rejection of claim 17 under 35 U.S.C. 101 is withdrawn in view of applicant's amendments/remarks.
Response to Arguments
5. Applicant’s argument filed on 01/26/2026 with respect claims 1-17 have been fully considered but they are not persuasive.
The applicant contends that the office action fails to teach or suggest the limitation of " reading two sets of burst data from a first storage channel and reading two sets of burst data from a second storage channel to obtain four sets of burst data." As recited in claims 1 and 14.
Examiner respectfully disagrees and asserts the reference of Olbrich et al. (US 2016/0299812 A1) in paragraphs [0051], [0058], [0134], and Fig. 9B teaches the such limitation. For example, (C1) Some implementations include a method of reading data stored in a non-volatile storage device having a plurality of physical memory portions having a predefined sequence of physical locations in one or more non-volatile memory devices of the storage device. In some implementations, the method includes, executing a command for reading a requested logical group of data having a specified logical address, including mapping the logical address to one or more physical locations in the storage device. Furthermore, in accordance with a first determination that the one or more physical locations in the storage device correspond to a single physical memory portion, data is read from the single physical memory portion, which includes the requested logical group of data, and the requested logical group of data is returned. In accordance with a second determination that the one or more physical locations in the storage device correspond to two physical memory portions at sequential physical locations in the predefined sequence of physical locations, a single sequential read operation is used to read data from the two physical memory portions, which together include the requested logical group of data, and the requested logical group of data is returned. In accordance with a third determination that the one or more physical locations in the storage device correspond to two physical memory portions at non-sequential physical locations in the predefined sequence of physical locations, two read operations are used to read data from the two non-sequential physical memory portions, which together include the requested logical group of data, and the requested logical group of data is returned. See paragraph [0051].
In some embodiments of the method of any of C1 to C7, in accordance with the second determination, reading data from the two physical memory portions includes: reading data from a first plurality of codewords stored in one of the two physical memory portions; and reading data from a second plurality of codewords stored in the other of the two physical memory portions, wherein each codeword of the first plurality of codewords have a first codeword length, and each codeword of the second plurality of codewords have a second codeword length, distinct from the first codeword length. See paragraph [0058].
[0134] However, in a second example, if it is determined that a requested logical group of data has one or more physical locations in the storage device corresponding to two physical memory portions having sequential physical locations, a single sequential read operation is performed to return the requested logical group of data. In contrast to a read operation for reading data from a single physical memory portion (as described in the example above), in some implementations, a sequential read operation includes reading data from (i.e., reading all or a subset of all codewords stored in) multiple physical memory portions having sequential physical locations. For example, logical group 606-3 corresponds to codewords 604-4 and 604-5, where codeword 604-4 is physical located on physical page 602-1 on word line 600-1, and codeword 604-5 is physically located on physical page 602-2 on word line 600-1. Although codewords 604-4 and 604-5 are located in different physical memory portions, the physical memory portions have sequential physical locations, and thus a single sequential read operation is executed to read the requested data (e.g., a single sequential read operation for retrieving and decoding all codewords across physical pages 602-1 and 602-2 to read the requested data for logical group 606-3). Consequently, all or a subset of all codewords 604-1 through 604-7 across physical pages 602-1 and 602-2 are retrieved by storage medium I/O 128 (FIG. 1) and provided to decoder 127, where decoded data corresponding to requested logical group 606-3 is made available to computer system 110. By performing a single sequential read operation, fewer read operations are required and system efficiency is thereby improved in comparison with implementations in which reading a logical group of data stored in two or more sequential physical memory portions (e.g., logical group 606-3) is read by performing a plurality of separate read operations (e.g., one read operation to read page 602-1 and another to read page 602-2). See paragraph [0134]. Also see Fig. 9B printed below for your convenience.
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As been described above, it would have been obvious to one of ordinary skill in the art that the group of data can be two or more data that have been read from two different storages to obtain group of data [one or more physical locations] not from a single logical data group as the applicant alleged. Emphasis added.
Also, the applicant contends that the cited references fail to teaches or suggest “wherein a total bit width of the m check symbols is eight times a bit width of one error correcting symbol.” As recited in claims 1 and 14.
The examiner respectfully disagrees and asserts the reference of Zhang et al. (US 20190034271 A1) teaches in paragraph [0048] and Fig. 3 such feature. For example, Optionally, in an embodiment, when n=6, data dies and an ECC die are DDR dies that each have a data bit width of 16 bits, in a data processing apparatus, the data dies are four DDR dies that each have a data bit width of 16 bits, and an ECC die is one DDR die that has a data bit width of 16 bits. In this case, the data processing apparatus according to this embodiment of this application may be a data processing apparatus shown in FIG. 5. As shown in FIG. 5, a type 1 interface of a first checking module is connected to data interfaces of a first data die and a second data die among the data dies using a DDR PHY, and a type 1 interface of the second checking module is connected to data interfaces of a third data die and a fourth data die among the data dies using the DDR PHY. A DDR controller herein includes two checking modules. Generally, in other approaches data processing apparatus includes only one checking module. In the other approaches data processing apparatus, the checking module obtains 64 bits of data from a cache module, generates an 8-bit ECC check code during a process of checking the 64 bits of data, separately stores the 64 bits of data in four data dies, and stores the 8-bit ECC check code in an ECC die. In this case, only one half of storage space of the ECC die is used to store the 8-bit ECC check code, and the other half of storage space is in an idle state. Therefore, the storage space is not fully utilized. A DDR controller of the data processing apparatus in this embodiment of this application has two checking modules. During ECC checking on 64 bits of data, the 64 bits of data can be divided into two groups, and each group has 32 bits of data, the two checking modules (that is, the first checking module and the second checking module) perform checking on two groups of 32 bits of data, respectively. During checking, to improve checking accuracy, the first checking module and the second checking module each generate an 8-bit ECC check code when checking respective 32 bits of data. After checking is completed, the 64 bits of data are still stored in the four data dies, and ECC check codes of 16 bits in total are stored in the ECC die. Compared with the other approaches data processing apparatus, a quantity of ECC check codes generated in the data processing apparatus in this embodiment of this application is twice of that generated in the other approaches data processing apparatus. For the other approaches data processing apparatus, the 8-bit ECC check code can be used to correct an error of 1 bit and detect an error of more than 2 bits in the 64 bits of data, whereas in this embodiment of this application, because ECC check codes are increased to 16 bits, the ECC check codes of 16 bits in total can be used to correct an error of 2 bits and detect an error of more than 4 bits in the 64 bits of data. Therefore, the data processing apparatus in this embodiment of this application not only improves checking accuracy, but also fully utilizes surplus storage space of the ECC die. For the Applicant’s convenience, see Fig. 3 is reproduced below.
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As been noted above and seen in Fig. 3, the 64 bits encoded data is eight times of 8-bit error correction which is eight times a bit width of one error correcting symbol, the claim feature of the total bit width of the m check symbols is eight times a bit width of one error correcting symbol is extremely board because no specific number been recited. For example, the if total bit width of the m check symbols of encoded data 32 bits, then the error correcting symbol should be 4 bits (4*8 bits=32 bits which is eight times), or can if total bit width of the m check symbols of encoded data 64 bits, then the error correcting symbol should be 8 bits (8*8 bits=64 bits which is eight times). Emphasis added.
Claim Objections
6. Claims 9-12 is/are objected to because of the following informalities:
The mathematic equations that included in claims 9-12 are blurred. Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
7. Claims 1, 2, and 14-17 are rejected under 35 U.S.C. 103 (a) as being unpatentable over Olbrich et al. (US 2016/0299812 A1) "herein after as Olbrich" in view of Zhang et al. (US 20190034271 A1)"herein after as Zhang."
As per claim 1: Olbrich substantially teaches or discloses a data processing method, comprising (see Fig. 9B): reading two sets of burst data from a first storage channel and reading two sets of burst data from a second storage channel to obtain four sets of burst data (see paragraph [0051], herein executing a command for reading a requested logical group of data having a specified logical address, including mapping the logical address to one or more physical locations in the storage device, paragraph [0058], herein reading data from a first plurality of codewords stored in one of the two physical memory portions; and reading data from a second plurality of codewords stored in the other of the two physical memory portions, paragraph [0134], herein reading a logical group of data stored in two or more sequential physical memory portions (e.g., logical group 606-3) is read by performing a plurality of separate read operations (e.g., one read operation to read page 602-1 and another to read page 602-2), and Fig. 9B steps 928 & 930 [Examiner notes: it would have been obvious to one of ordinary skill in the art that the group of data can be two or more data that have been read from two different storages to obtain group of data (one or more physical locations)]), wherein the four sets of burst data correspond to encoded data stored in the first storage channel and the second storage channel, the encoded data is obtained by encoding k data symbols that are written into the first storage channel and the second storage channel, and the encoded data comprises the k data symbols and m check symbols (see paragraph [0079], herein encoder 126 encodes data by applying an error control code to produce a codeword, which is subsequently stored in one or more NVM devices 140 of one or more memory channels 150. Codewords produced by the encoder include both data (sometimes herein called the encoded data) and corresponding error correction bits (sometimes called parity values, parity bits, or syndrome values); organizing the four sets of burst data into a group of error correcting codewords, wherein the group of error correcting codewords comprises k read-back data symbols and m read-back check symbols (see paragraph [0079], herein encoders can be configured to produce codewords having a particular code rate (e.g., ratio of data bits in a codeword to the size of the codeword) and codeword structure (e.g., length, in bits, of the codeword; optionally, the codeword structure also includes information about where, within the codeword, the error correction bits are located)); and performing a decoding operation based on the group of error correcting codewords to obtain an error-corrected symbol (see paragraph [0079], herein When the encoded data (e.g., one or more codewords) is read from NVM devices 140, the decoder applies a decoding process to the encoded data to recover the data, and to correct errors in the recovered data within the error correcting capability of the error control code). Olbrich does not explicitly teach wherein a total bit width of the m check symbols is eight times a bit width of one error correcting symbol. However, Zhang in the same the field of endeavor teaches wherein a total bit width of the m check symbols is eight times a bit width of one error correcting symbol (see paragraph [0048], herein the first checking module and the second checking module each generate an 8-bit ECC check code when checking respective 32 bits of data. After checking is completed, the 64 bits of data are still stored in the four data dies, and ECC check codes of 16 bits in total are stored in the ECC die --- the 8-bit ECC check code can be used to correct an error of 1 bit and detect an error of more than 2 bits in the 64 bits of data, and Fig. 3 [Examiner notes: As been noted above and seen in Fig. 3, the 64 bits encoded data is eight times of 8-bit error correction]). Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, to modify the system of Olbrich with the teachings of Zhang by including total bit width of the m check symbols is eight times a bit width of one error correcting symbol. This modification would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, because one of ordinary skill in the art would have recognized the total bit width of the m check symbols is eight times a bit width of one error correcting symbol would have increased error correcting encoding capability.
As per claim 2: Olbrich teaches that wherein organizing the four sets of burst data into the group of error correcting codewords, comprises: combining burst data, corresponding to a same memory device, in the two sets of burst data that are read from the first storage channel into one error correcting codeword symbol to obtain a first-part error correcting codeword (see paragraph [0172], herein reading data from the two physical memory portions (step 922) includes reading (928) data from a first plurality of codewords stored in one of the two physical memory portions); combining burst data, corresponding to a same memory device, in the two sets of burst data that are read from the second storage channel into one error correcting codeword symbol to obtain a second-part error correcting codeword (see paragraph [0172], herein reading (930) data from a second plurality of codewords stored in the other of the two physical memory portions, wherein each codeword of the first plurality of codewords have (932) a first codeword length, and each codeword of the second plurality of codewords have a second codeword length, distinct from the first codeword length); and combining the first-part error correcting codeword and the second-part error correcting codeword (see paragraph [0105], herein referring to the examples of FIG. 3, and the corresponding error correction formats shown in FIG. 4A used to produce the codewords (codewords 300-1 through 300-8 corresponding to error correction formats “1” through “8,” respectively), the error correction format with which codeword 300-6 is produced (e.g., LDPC algorithm, code rate 0.93, codeword length 4 KB) provides a higher error correction capability than the error correction format with which codeword 300-4 is produced (e.g., BCH algorithm, code rate 0.94, code length 4 KB)., and Fig. 4).
As per claim 14: Olbrich substantially teaches or discloses a data processing apparatus, comprising (see Fig. 1, data storage system 100): a hardware processor, configured to: read two sets of burst data from a first storage channel and reading two sets of burst data from a second storage channel to obtain four sets of burst data (see paragraph [0051], herein executing a command for reading a requested logical group of data having a specified logical address, including mapping the logical address to one or more physical locations in the storage device, paragraph [0058], herein reading data from a first plurality of codewords stored in one of the two physical memory portions; and reading data from a second plurality of codewords stored in the other of the two physical memory portions, paragraph [0034], herein reading a logical group of data stored in two or more sequential physical memory portions (e.g., logical group 606-3) is read by performing a plurality of separate read operations (e.g., one read operation to read page 602-1 and another to read page 602-2), and Fig. 9B steps 928 & 930 [Examiner notes: it would have been obvious to one of ordinary skill in the art that the group of data can be two or more data that have been read from two different storages to obtain group of data]), wherein the four sets of burst data correspond to encoded data stored in the first storage channel and the second storage channel, the encoded data is obtained by encoding k data symbols that are written into the first storage channel and the second storage channel, and the encoded data comprises the k data symbols and m check symbols, (see paragraph [0079], herein encoder 126 encodes data by applying an error control code to produce a codeword, which is subsequently stored in one or more NVM devices 140 of one or more memory channels 150. Codewords produced by the encoder include both data (sometimes herein called the encoded data) and corresponding error correction bits (sometimes called parity values, parity bits, or syndrome values); and organize the four sets of burst data into a group of error correcting codewords, wherein the group of error correcting codewords comprises k read-back data symbols and m read-back check symbols (see paragraph [0079], herein encoders can be configured to produce codewords having a particular code rate (e.g., ratio of data bits in a codeword to the size of the codeword) and codeword structure (e.g., length, in bits, of the codeword; optionally, the codeword structure also includes information about where, within the codeword, the error correction bits are located)); perform a decoding operation based on the group of error correcting codewords to obtain an error-corrected symbol (see paragraph [0079], herein When the encoded data (e.g., one or more codewords) is read from NVM devices 140, the decoder applies a decoding process to the encoded data to recover the data, and to correct errors in the recovered data within the error correcting capability of the error control code). Olbrich does not explicitly teach wherein a total bit width of the m check symbols is eight times a bit width of one error correcting symbol. However, Zhang in the same the field of endeavor teaches wherein a total bit width of the m check symbols is eight times a bit width of one error correcting symbol (see paragraph [0048], herein the first checking module and the second checking module each generate an 8-bit ECC check code when checking respective 32 bits of data. After checking is completed, the 64 bits of data are still stored in the four data dies, and ECC check codes of 16 bits in total are stored in the ECC die, and Fig. 3). Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, to modify the system of Olbrich with the teachings of Zhang by including total bit width of the m check symbols is eight times a bit width of one error correcting symbol. This modification would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, because one of ordinary skill in the art would have recognized the total bit width of the m check symbols is eight times a bit width of one error correcting symbol would have increased error correcting encoding capability.
As per claim 15: Olbrich teaches that a storage system (see Fig. 1, data storage system 100), comprising: the processing apparatus according to claim 14; and a storage unit (see Fig. 1, memory channels 150).
As per claim 16: Olbrich teaches that an electronic apparatus, comprising: a processor; and a memory, on which instructions are stored, wherein the instructions, when executed by the processor, cause the processor to execute the processing method according to claim 1 (see paragraph [0047], herein any of the methods B1-B14 are performed by a storage device or system that includes non-volatile memory (NVM) having a plurality of distinct memory portions in a plurality of non-volatile memory (NVM) devices, and one or more memory controllers, the one or more memory controllers including one or more processors and memory for storing one or more programs for execution by the one or more processors, the one or more programs including instructions for performing the method of any of B1-B1, paragraph [0067], and Fig. 1).
As per claim 17: Olbrich teaches that a non-transient computer-readable storage medium, on which instructions are stored, wherein the instructions, when executed by a processor, cause the processor to execute the processing method according to claim 1 (see paragraph [0032], herein a non-transitory computer readable storage medium stores one or more programs for execution by one or more processors, paragraph [0067], and Fig. 1)).
Examiner Notes
8. When amending the claims, applicants are respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
Allowable Subject Matter
9. Claim 3 is/are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Dependent claims 4-13 depend from claim 3 and inherently include limitations therein and therefore are allowed as well.
Prior Art
10. The prior art of record, considered pertinent to the applicant’s disclosure, is listed in the attached PTO-892 form.
Conclusion
11. THIS ACTION IS MADE FINAL; Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to OSMAN ALSHACK whose telephone number is (571)272-2069.
The examiner can normally be reached on MON-FRI 8:30 AM-5:00 PM EST, also please fax interview request to (571) 273- 2069.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, ALBERT DECADY can be reached on 5712723819. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/OSMAN ALSHACK/
Examiner, Art Unit 2112
/ALBERT DECADY/Supervisory Patent Examiner, Art Unit 2112