DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-3, 13-15 and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yamada et al. WO 2020/075433 A1 ( US 2021/0232894 A1 is an equivalent and used for the rejection), and further in view of Myers et al. (US 2012/0286824 A1).
Regarding claim 1, Yamada teaches a neural network circuit comprising:
a convolution operation circuit that performs a convolution operation on input data (Fig. 3, Convolutional operation S3); and
a quantization operation circuit that performs a quantization operation on convolution operation output data from the convolution operation circuit (Fig. 3, Conversion-quantization processing S5);
Yamada has an inherent clock signal that is used to synchronize the operation. Yamada is silent in teaching the convolution operation circuit, when waiting to execute a next convolution operation from a series of convolution operations being executed, enables clock gating of a first clock supplied to at least a portion of the convolution operation circuit.
Myers teaches a clock gating circuit unit which will enable clock gating of first clock supplied to the integrated circuit during the operation of the circuit and to disable the clock gating during the low power mode (abstract).
It would have been obvious to a person with the ordinary skill in the art before the effective filling date of the claimed invention to use clock gating signals in order to disable the convolution circuitry during the low power mode and reduce power consumption and enable the clock gating circuit during normal operation.
Regarding claim 2, Yamada and Myers further teaches the neural network circuit according to claim 1, wherein the quantization operation circuit, when waiting to execute a next quantization operation from a series of quantization operations being executed, enables clock gating of a second clock supplied to at least a portion of the quantization operation circuit (Myers teaches the clock gating circuit will be enabled for the integrated circuit to operate normal during the normal operation. And to disable the clock gating during low power mode to reduce power consumption).
Regarding claim 3, Yamada and Myers further teaches the neural network circuit according to claim 2, further having:
a first memory that stores the input data (Fig. 1, Input Buffer 10); and
a second memory that stores the convolution operation output data (Output buffer 15);
wherein the convolution operation circuit, when executing the convolution operation on the input data stored in the first memory, disables clock gating of the first clock; and the quantization operation circuit, when executing the quantization operation on the convolution operation output data stored in the second memory, disables clock gating of the second clock (Myers teaches the feature of powering down the circuitries when they are performing the operation is disabled) .
Regarding claim 13, Yamada and Myers further teaches the neural network circuit according to claim 1, comprising a plurality of operation cores having the convolution operation circuit and the quantization operation circuit; wherein the convolution operation circuit in at least one of the operation cores, when waiting to execute the convolution operation, enables clock gating of the first clock supplied to at least a portion of the convolution operation circuit (Myers teaches the clock gating circuit will be enabled for the integrated circuit to operate normal during the normal operation. And to disable the clock gating during low power mode to reduce power consumption).
Regarding claims 14-17, the claims have similar limitations as claims 1-3 and 13. Therefore, the claims are rejected under the same grounds of rejection.
Allowable Subject Matter
Claims 4-12 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
After further search and consideration it is determined that the prior art of record neither anticipated nor renders obvious the claimed subject matter of the instant application as a whole either taken alone or in combination, in particular, prior art of record does not teach, the following limitation(s) in combination with the remaining claimed limitation:
With regards to claim 4, wherein the quantization operation output data from the quantization operation circuit is stored in the first memory; and the quantization operation output data stored in the first memory is input, as the input data, to the convolution operation circuit.
With regards to claim 5, a third read semaphore that restricts reading from the first memory by the convolution operation circuit; and a second write semaphore that restricts writing into the second memory by the convolution operation circuit; wherein the convolution operation circuit, when waiting to execute the convolution operation based on the third read semaphore and the second write semaphore, enables clock gating of the first clock supplied to at least a portion of the convolution operation circuit.
Response to Arguments
Applicant's arguments filed 05/13/2026 have been fully considered but they are not persuasive.
Applicant’s representative argues on top of page 8 “Applicant submits that Yamada fails to disclose the "convolution operation circuit" and the "quantization operation circuit" as recited by Applicant's independent claim 1. In contrast, Yamada merely discloses a convolution operation unit and processing unit, which are units of software. Applicant submits that units of software do not teach or suggest the "convolution operation circuit" and the "quantization operation circuit" as recited by Applicant's independent claim 1.”
The examiner respectfully does not agree with the applicant’s representative statement. The convolution operation in step (Fig. 3, S3) and Conversion Quantization Processing (S5) are processed by Convolutional Operation Unit (Fig. 1, 12) and the Processing Unit (Fig. 1, 14), which these units are part of the CNN Processing Apparatus, which are circuit units. In addition, the term clock gating enabled, it means the gated clock GC4 will be stopped and it will turn off circuitry to reduce power consumption, see ¶0202 of the original filed specification of the current invention. Myers teaches the same concept of powering down circuitries when they are not in used by having a disable clock signal, The disable clock signal enables the power gating to reduce the power consumption. When the clock signal is enabled, the power gating is disabled so the circuity is operating in a normal operation. Therefore, the claimed features are taught by Yamada in view of Myers.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KHAMDAN N ALROBAIE whose telephone number is (571)270-7099. The examiner can normally be reached Monday to Thursday (8AM till 6PM).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Richard Elms can be reached at (571) 272-1869. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/Khamdan N. Alrobaie/ Primary Examiner, Art Unit 2824
Prosecution Insights