DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d).
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 04/04/2024 and 12/12/2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-2, 13-15 and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yamada et al. WO 2020/075433 A1 ( US 2021/0232894 A1 is an equivalent and used for the rejection), and further in view of Myers et al. (US 2012/0286824 A1).
Regarding claim 1, Yamada teaches a neural network circuit comprising:
a convolution operation circuit that performs a convolution operation on input data (Fig. 3, Convolutional operation S3); and
a quantization operation circuit that performs a quantization operation on convolution operation output data from the convolution operation circuit (Fig. 3, Conversion-quantization processing S5);
Yamada has an inherent clock signal that is used to synchronize the operation. Yamada is silent in teaching the convolution operation circuit, when waiting to execute the convolution operation, enables clock gating of a first clock supplied to at least a portion of the convolution operation circuit.
Myers teaches a clock gating circuit unit which will enable clock gating of first clock supplied to the integrated circuit during the operation of the circuit and to disable the clock gating during the low power mode (abstract).
It would have been obvious to a person with the ordinary skill in the art before the effective filling date of the claimed invention to use clock gating signals in order to disable the convolution circuitry during the low power mode and reduce power consumption and enable the clock gating circuit during normal operation.
Regarding claim 2, Yamada and Myers further teaches the neural network circuit according to claim 1, wherein the quantization operation circuit, when waiting to execute the quantization operation, enables clock gating of a second clock supplied to at least a portion of the quantization operation circuit (Myers teaches the clock gating circuit will be enabled for the integrated circuit to operate normal during the normal operation. And to disable the clock gating during low power mode to reduce power consumption).
Regarding claim 13, Yamada and Myers further teaches the neural network circuit according to claim 1, comprising a plurality of operation cores having the convolution operation circuit and the quantization operation circuit; wherein the convolution operation circuit in at least one of the operation cores, when waiting to execute the convolution operation, enables clock gating of the first clock supplied to at least a portion of the convolution operation circuit (Myers teaches the clock gating circuit will be enabled for the integrated circuit to operate normal during the normal operation. And to disable the clock gating during low power mode to reduce power consumption).
Regarding claims 14-15 and 17, the claims have similar limitations as claims 1-2 and 13. Therefore, the claims are rejected under the same grounds of rejection.
Allowable Subject Matter
Claims 3-12 and 16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
After further search and consideration it is determined that the prior art of record neither anticipated nor renders obvious the claimed subject matter of the instant application as a whole either taken alone or in combination, in particular, prior art of record does not teach, the following limitation(s) in combination with the remaining claimed limitation:
With regards to claim 3, a first memory that stores the input data; and a second memory that stores the convolution operation output data; wherein the convolution operation circuit, when executing the convolution operation on the input data stored in the first memory, disables clock gating of the first clock; and the quantization operation circuit, when executing the quantization operation on the convolution operation output data stored in the second memory, disables clock gating of the second clock.
With regards to claim 16, wherein the neural network circuit further has a first memory that stores the input data; and a second memory that stores the convolution operation output data; and the neural network circuit control method comprises the convolution operation circuit, when executing the convolution operation on the input data stored in the first memory, disabling clock gating of the first clock; and the quantization operation circuit, when executing the quantization operation on the convolution operation output data stored in the second memory, disabling clock gating of the second clock.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KHAMDAN N ALROBAIE whose telephone number is (571)270-7099. The examiner can normally be reached Monday to Thursday (8AM till 6PM).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Richard Elms can be reached at (571) 272-1869. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Khamdan N. Alrobaie/ Primary Examiner, Art Unit 2824