DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-4,6,7,9,13,16,19,21,23,26-31,33 is/are rejected under 35 U.S.C. 102 (a1) as being anticipated by Carlson et al., (Carlson) USPAT 9,886,275.
Regarding claim 1, Carlson shows in FIG. 1-5, a multi-core chip, comprising: a first core layer (310a) (7:50-60) including: a first operation area (304) (6:60-66) in which a first operation circuit is generated, and a first die-to-die area in which a first transceiver circuit (319)(7:35-45) is generated; and a second core layer (310b) including: a second operation area in which a second operation circuit is generated, and a second die-to-die area in which a second transceiver circuit (319a) is generated, wherein the first core layer and the second core layer are vertically stacked (See FIG. 3A), and the first operation circuit and the second operation circuit transfer data (data processor)(7:20-30) between layers through the first transceiver circuit and the second transceiver circuit.
Regarding claim 2, Carlson shows in FIG. 1-5, a multi-core chip according to claim 1, connected to an off-chip memory (3:60-66) and comprising a memory layer, wherein the memory layer includes: a memory area (310a-310c have a memory area) (7:45-65) generated with a storage unit (4:1-15) for temporarily storing operation results of the first operation circuit and the second operation circuit; an input/output area (on 300, path connected to 319)(7:35-45) generated with an input/output circuit to serve as an interface for the multi-core chip to communicate with the outside (Id.); and a physical area generated with a physical access circuit to access the off-chip memory (5:20-30).
Regarding claim 3, Carlson shows in FIG. 1-5, a multi-core chip wherein the memory layer (on 310a-310c) (3:60-66) is located between the first core layer and the second core layer (310b), and the memory layer is generated with a through silicon via (TSV) (of 319a) (7:35-45) for electrically connecting the first transceiver circuit and the second transceiver circuit.
Regarding claim 4, Carlson shows in FIG. 1-5, a multi-core chip wherein the memory area is located between the first core layer (310a) and the second core layer (310b), and the second core layer is generated with a TSV (TSV) (of 319a) (7:35-45) for electrically transferring data of the input/output circuit or data of the physical access circuit (TSV) (of 319a) (7:35-45).
Regarding claims 6,7,9,13,16,19,21,23, Carlson shows in FIG. 1-5, a multi-core chip further comprising: a first memory layer including a first memory area (on 310a-c) (3:60-66) generated with a storage unit (3:60-66) for temporarily storing operation results of the first operation circuit (3:60-66); and a second memory layer (310b) (3:60-66) including a second memory area generated with a storage unit (4:1-15) for temporarily storing operation results of the second operation circuit (4:1-15), wherein the first core layer (310a), the first memory layer, the second core layer (310b) and the second core layer are stacked in sequence, and the first memory layer is generated with a transceiver TSV (319a) (7:35-45) for electrically connecting the first transceiver circuit and the second transceiver circuit (7:35-45); wherein the first memory layer also includes a first input/output area (7:35-45) generated with a first input/output circuit to serve as an interface for the multi-core chip to communicate with the outside, and the second core layer (310b) and the second memory layer are generated with input/output TSVs for electrically transferring data of the first input/output circuit, and wherein the second memory layer also includes a second input/output area generated with a second input/output circuit (319) (7:35-45) electrically connected with outside of the multi-core chip through an input/output TSV (319a) (7:35-45); connected to an off-chip memory, wherein the first memory layer also includes a first physical area generated with a physical access circuit (7:35-45), and the second core layer and the second memory layer are generated with a physical TSV for electrically transferring operation results of the first operation circuit to the off-chip memory (7:35-45), wherein the second memory layer also includes a second physical area generated with a second physical access circuit for transferring the operation results of the second operation circuit to the off-chip memory through a physical TSV (7:35-45), and wherein the first core layer and the first memory layer are manufactured by face-to-face bonding, and wherein the first memory layer and the second core layer are manufactured by back-to-back bonding, and the second core layer and the second memory layer are manufactured by face-to-face bonding; further comprising a third memory layer (7:35-45), which includes a third memory area (310c) generated with a storage unit for temporarily storing the operation results of the first operation circuit, wherein the third memory layer is located above the first core layer, wherein the third core layer (on 310c) and the first core layer are manufactured by face-to-face or face-to-back bonding, a fourth memory (9:1-10) area generated with a storage unit for temporarily storing the operation results of the second operation circuit (9:1-10), wherein the fourth memory layer (9:1-10) is located between the first memory layer and the second core layer, and the fourth memory layer is generated with a transceiver TSV for electrically connecting the first transceiver circuit and the second transceiver circuit (9:1-10); wherein the first memory layer also includes a first input/output area generated with a first input/output circuit to serve as an interface for the multi-core chip to communicate with the outside (7:35-45), and the fourth memory layer, the second core layer and the second memory layer are generated with an input/output TSV for electrically transferring data of the first input/output circuit, wherein the first memory layer also includes a first physical area generated with a physical access circuit (7:35-45), and the fourth memory layer, the second core layer and the second memory layer are generated with a physical TSV for electrically transferring operation results of the first operation circuit to an off-chip memory, and wherein the first core layer and the first memory layer are manufactured by face-to-face bonding (7:35-45), the first memory layer and the fourth core layer are manufactured by back-to-back bonding, the fourth memory layer (9:1-10)and the second core layer are manufactured by face-to-face bonding, and the second core layer and the second memory layer are manufactured by face-to-back bonding(7:35-45) (9:1-10); further comprising a third memory layer, which includes a third memory area generated with a storage unit for temporarily storing the operation results of the first operation circuit or the second operation circuit (7:35-45) (9:1-10), wherein the third memory layer is located under the second core layer, wherein the third memory layer also includes an input/output area generated with an input/output circuit to serve as an interface for the multi-core chip to communicate with the outside (7:35-45) (9:1-10); connected to an off-chip memory, wherein the third memory layer also includes a physical area generated with a physical access circuit for transferring the operation results of the first operation circuit or the second operation circuit to the off-chip memory (7:35-45) (9:1-10), wherein the first core layer and the first memory layer are manufactured by face-to-face bonding (7:35-45) (9:1-10), the first memory layer and the second core layer are manufactured by back-to-back bonding, the second core layer and the second memory layer are manufactured by face-to-face bonding, and the second core layer and the third memory layer are manufactured by face-to-back bonding (7:35-45) (9:1-10); wherein each layer is packaged by flip chip ball grid array or packaged by CoWoS (7:35-45) (9:1-10).
Regarding claim 26, Carlson shows in FIG. 1-5, a board card, comprising a multi-core chip, the multi-core chip comprising: a first core layer (310a) including: a first operation area in which a first operation circuit is generated, and a first die-to-die area (on 310a) in which a first transceiver circuit (319a) (310a-310c have a memory area) (7:45-65) is generated; and a second core layer including: a second operation area in which a second operation circuit is generated, and a second die-to-die area (310b, 319) in which a second transceiver circuit is generated, wherein the first core layer (310a) and the second core layer (310b) (310a-310c have a memory area) (7:45-65) are vertically stacked, and the first operation circuit and the second operation circuit transfer data between layers through the first transceiver circuit and the second transceiver circuit (7:45-65).
Regarding claim 27, Carlson shows in FIG. 1-5, a method for manufacturing a multi-core chip, comprising: generating a first core layer (310a) including a first operation area in which a first operation circuit is generated, and a first die-to-die are in which a first transceiver circuit is generated (310a-310c have a memory area) (7:45-65) ; and generating a second core layer (310b) including a second operation area in which a second operation circuit is generated (7:45-65) , and a second die-to-die area in which a second transceiver circuit is generated (310a-310c have a memory area) (7:45-65) , wherein the first core layer and the second core layer are vertically stacked, and the first operation circuit and the second operation circuit transfer data between layers through the first transceiver circuit and the second transceiver circuit (310a-310c have a memory area) (7:45-65).
Regarding claim 28, Carlson shows in FIG. 1-5, a method, wherein the multi-core chip is connected to an off-chip memory, and the method further comprises generating a memory layer between the first core layer and the second core layer (310a) (7:45-65) , wherein the memory layer includes: a memory area generated with a storage unit for temporarily storing operation results of the first operation circuit and the second operation circuit(7:45-65); an input/output area generated with an input/output circuit to serve as an interface for the multi-core chip to communicate with the outside (7:45-65); and a physical area generated with a physical access circuit to access the off-chip memory (3:60-66) (7:45-65).
Regarding claims 29-31,33, Carlson shows in FIG. 1-5, a method wherein steps of generating the memory layer includes generating a TSV in the memory layer for electrically connecting the first transceiver circuit (part of 310a) and the second transceiver circuit (on 310b); further comprising: generating a first memory layer including a first memory area (310a-310c have a memory area) (7:45-65); generated with a storage unit for temporarily storing operation results of the first operation circuit; and generating a second memory layer (on 310b) (7:45-65)including a second memory area generated with a storage unit for temporarily storing operation results of the second operation circuit, wherein the first core layer, the first memory layer (7:45-65)r, the second core layer and the second core layer are stacked in sequence (7:45-65), and steps of generating the first memory layer includes generating a transceiver TSV in the first memory layer for electrically connecting the first transceiver circuit and the second transceiver circuit (310b) (7:45-65); further comprising generating a third memory layer including a third memory area generated with a storage unit for temporarily storing operation results of the first operation circuit, wherein the third memory layer is located above the first core layer (310a), and generating a fourth memory layer including a fourth memory area (9:1-6) generated with a storage unit for temporarily storing the operation results of the second operation circuit, wherein the fourth memory layer is located between the first memory layer and the second core layer (9:1-6), and steps of generating the fourth memory layer includes generating a transceiver TSV in the fourth memory layer for electrically connecting the first transceiver circuit and the second transceiver circuit (9:1-6); further comprising generating a third memory layer including a third memory area generated with a storage unit for temporarily storing operation results of the first operation circuit or the second operation circuit (9:1-6), wherein the third memory layer (310c) is located under the second core layer (9:1-6).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MARC-ANTHONY ARMAND whose telephone number is (571)272-5178. The examiner can normally be reached 8am-5pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven B Gauthier can be reached at 571-270-0373. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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MARC - ANTHONY ARMAND
Primary Examiner
Art Unit 2813
/MARC-ANTHONY ARMAND/Primary Examiner, Art Unit 2813
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