Prosecution Insights
Last updated: July 17, 2026
Application No. 18/698,645

WINDOW CAVITY WAFERS

Non-Final OA §102§103
Filed
Apr 04, 2024
Priority
Oct 05, 2021 — provisional 63/252,327 +1 more
Examiner
JONES, ERIC W
Art Unit
2892
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
MATERION Corporation
OA Round
1 (Non-Final)
62%
Grant Probability
Moderate
1-2
OA Rounds
10m
Est. Remaining
79%
With Interview

Examiner Intelligence

Grants 62% of resolved cases
62%
Career Allowance Rate
434 granted / 702 resolved
-6.2% vs TC avg
Strong +17% interview lift
Without
With
+17.3%
Interview Lift
resolved cases with interview
Typical timeline
3y 1m
Avg Prosecution
32 currently pending
Career history
728
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
94.0%
+54.0% vs TC avg
§102
3.9%
-36.1% vs TC avg
§112
0.6%
-39.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 702 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Priority Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55. Information Disclosure Statement The information disclosure statements (IDS) submitted on 4/4/2024 and 4/24/2024 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. Specification The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. The following title is suggested: BONDED WINDOW CAVITY WAFERS. Preliminary Amendment Applicant's 4/4/2024 Preliminary Amendment to: 1. Amend the Claims. 2. Amend the Specification is acknowledged and accepted by the Office. Claims Status Claims 1-3, 5-7, 10-18, 20-21 and 25-27 are currently pending and being examined. Claims 4, 8-9, 19 and 22-24 have been canceled by the 4/4/2024 Preliminary Amendment. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim 1 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Huang et al (US 2020/0051883 A1, hereafter Huang). Re claim 1, Huang discloses in FIG. 2 a window cavity wafer (100), comprising: a window wafer (laminate 102/108/104; [0036]) including a window wafer substrate (102; [0042]) and one or more optical coatings (108; [0042]) disposed on one or more faces (backside) of the window wafer substrate (102); and a spacer wafer (laminate 106/108/110; [0036]) including a spacer wafer substrate (106; [0036]), wherein the spacer wafer (laminate 106/108/110) is wafer bonded (coupled by 105; [0036]) to the window wafer (laminate 102/108/104) to form the window cavity wafer (100), and wherein the window cavity wafer (100) includes metal frames (110; [0036] and [0047]). Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Claims 1-3, 6-7 and 10-13 are rejected under 35 U.S.C. 103 as being unpatentable over Steffanson (US 2018/0106682 A1) in view of Huang. Re claim 1, Steffanson discloses in FIG. 20B a window cavity wafer (701/102), comprising: a window wafer (double-side coated 701; [0102]) including a window wafer substrate (701; [0102]) and one or more optical coatings (unseen anti-reflection or filter layers; [0102]) disposed on one or more faces (double-sided; [0102]) of the window wafer substrate (701); and a spacer wafer (laminate 102/111; [0102]) including a spacer wafer substrate (102; [0102]), wherein the spacer wafer (laminate 102/111) is wafer bonded (wafer-level bonding; [0102]) to the window wafer (double-side coated 701) to form the window cavity wafer (701/102). But, Steffanson fails to disclose and wherein the window cavity wafer (701/102) includes metal frames. However, A. Steffanson discloses in FIG. 10 a window cavity wafer comprising: eutectic bonds between substrates ([0073]). And, B. Huang discloses in FIG. 2 a window cavity wafer comprising: wherein a window cavity wafer (100) includes metal frames (110; [0036] and [0047]-[0048]) for bonds between wafers (laminate 106/108/110 and 112; [0036]). Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the structure of Steffanson by using the eutectic bonding concept of Staffanson with the metal frames of Huang between the window and spacer wafers of Steffanson, such that the window cavity wafer (700) includes metal frames for the predictable result(s) of a hermetically sealed (Steffanson: [0070] and Huang: [0047]) window cavity wafer. Re claim 2, Steffanson discloses the window cavity wafer of claim 1, wherein the one or more optical coatings (anti-reflection or filter layers) comprises one or more of an antireflective coating ([0102]), an optical filter coating ([0102]), and/or a long-pass blocker coating. Re claim 3, Steffanson discloses the window cavity wafer of claim 1, wherein: the window wafer substrate (701) comprises one of: silicon (Si; [0102]), germanium (Ge; [0102]), borofloat glass, or sapphire. But, fails to disclose wherein: the window wafer substrate (701) has a thickness between 300 µm and 1000 µm; and/or the spacer wafer substrate (102) has a thickness between 100 µm and 500 µm, and the spacer wafer substrate (102) comprises one of: glass, sapphire, ceramic, silicon (Si), or metal alloy. However, Huang discloses the window wafer substrate (102) has a thickness between 300 µm and 1000 µm (0.1-1.7 mm; [0039]); and/or the spacer wafer substrate (106) comprises one of: glass, sapphire, ceramic, silicon (Si; [0041]), or metal alloy. Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the structure of Steffanson by using the window wafer substrate thickness of Huang for the window wafer substrate (701) of Steffanson to have a thickness between 300 µm and 1000 µm (0.1-1.7 mm); and/or using the spacer wafer substrate material of Huang such that the spacer wafer substrate (102) comprises silicon (Si), as part of the expected result of the hermetically sealed window cavity wafer discussed for claim 1. Re claim 6, Steffanson and Hunag disclose the window cavity wafer of claim 1, wherein one or more metal layers (Huang: 110; [0047]) are disposed (Steffanson: for eutectic bonding) on one or more faces (Steffanson: top and/or bottom planes) of the spacer wafer substrate (Steffanson: 102), as part of the expected result of the hermetically sealed window cavity wafer using eutectic bonding discussed for claim 1. Re claim 7, Steffanson and Hunag disclose the window cavity wafer of claim 6, wherein the one or more metal layers comprise seed layer stacks, the seed layer stacks comprising one of: (i) Cr + Ni + Au (Huang: [0047]); or (ii) Ti + Pt + Au (Huang: [0047]) formulated for the possibilities of Huang, as part of the expected result of the hermetically sealed window cavity wafer using eutectic bonding discussed for claim 1. Re claim 10, Steffanson discloses the window cavity wafer of claim 1, wherein the spacer wafer substrate (102) is perforated (through-etched; [0102]). Re claim 11, Steffanson discloses the window cavity wafer of claim 6. But, fails to the window cavity wafer further comprising: a metal plating layer disposed over one of the metal layers. However, Huang discloses the metals (110) may be electroplated ([0047]), and thus, comprising a metal plating layer disposed over one of the metal layers, as part of the expected result of the hermetically sealed window cavity wafer using eutectic bonding discussed for claim 1. Re claim 12, Steffanson discloses the window cavity wafer of claim 1, further comprising: a glass layer (111 as in FIG. 10; [0070]; [0073] and [0102]) disposed on the spacer wafer substrate (102). Re claim 13, Steffanson discloses the window cavity wafer of claim 1, further comprising: a getter (unseen; [0102]) disposed on the window wafer substrate (701). Steffanson does not explicitly disclose the getter disposed inside cavities of the window cavity wafer. However, it would have been obvious to place the getter such that is disposed inside cavities (through-etches of 102; [0102]) of the window cavity wafer (701), approximate encapsulated devices (1; [0102]) to remove unwanted gases or elements detrimental to maintaining the hermetic seals of the cavities enclosing the devices ([0101]). Claims 14-18, 20-21, 25-26; and 27 are rejected under 35 U.S.C. 103 as being unpatentable over Steffanson in view of Huang and Stark (US 2006/0191215 A1). Re claim 14, Steffanson discloses in FIGS. 20A-20B a method for forming a window cavity wafer (701/102), comprising: fabricating a window wafer (double-side coated 701 in FIG. 20A; [0102]) by: providing a window wafer substrate (701; [0102]) having two faces (upper/lower planes); polishing (double-sided; [0102]) one or more faces (upper/lower planes) of the window wafer substrate (701); and applying one or more optical coatings (unseen anti-reflection or filter layers in FIG. 20A; [0102]) to on one or more faces (upper/lower planes) of the window wafer substrate (701); fabricating a spacer wafer (laminate 102/111 in FIG. 20A; [0102]) separate from the window wafer (double-side coated 701 in FIG. 20A) by: providing a spacer wafer substrate (111; [0102]) having two faces (upper/lower planes); and forming an array of through-holes (through-etches in FIG. 20A; [0102]) in the spacer wafer substrate (111); bonding (wafer-level bonding in FIG. 20B; [0102]) the spacer wafer (laminate 102/111) to the window wafer (double-side coated 701 in FIG. 20A) to form the window cavity wafer (701/102). But, Steffanson fails to disclose etching one or more faces of the window wafer substrate (701); and forming discrete metal frames on a face of the window cavity wafer (701/102). However, A. Stark discloses a window cavity wafer method comprising: etching (PCM; [0243] and [0389]) one or more faces (exposed surfaces) of a window cavity wafer substrate (302 and 1722; [0243] and [0389]). And, B. Steffanson discloses in FIG. 10 a window cavity wafer comprising: eutectic bonds between substrates ([0073]). And, C. Huang discloses in FIG. 2 a window cavity wafer comprising: wherein a window cavity wafer (100) includes metal frames (110; [0036] and [0047]-[0048]) for bonds between wafers (laminate 106/108/110 and 112; [0036]). Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Steffanson by first applying the etching of the one or more faces of the window wafer substrate, of Park, to the window wafer substrate of Steffanson, facilitating separation of the window cavity wafer substrate bending instead of cutting (Stark; [0444]). And, then using the eutectic bonding concept of Steffanson with the metal frames of Huang between the window and spacer wafers of Steffanson, such that discrete metal frames are formed on a face of the window cavity wafer (700) for the predictable result(s) of a hermetically sealed (Steffanson: [0070] and Huang: [0047]) window cavity wafer. Re claim 15, Steffanson and Huang disclose the method of claim 14, further comprising: depositing one or more metal layers (Huang) on one or more faces of the spacer wafer substrate (see claim 6), as part of the method of forming the hermetically sealed window cavity wafer discussed for claim 14. Re claim 16, Steffanson discloses the method of claim 15, further comprising: depositing a getter inside cavities of the window cavity wafer (see claim 13); and bonding (wafer-level bonding in FIG. 20A; [0102]) the spacer wafer substrate (102) to a readout integrated circuit (optical readout of 1 on 111; [0103]), as part of the method of forming the hermetically sealed window cavity wafer discussed for claim 14. Steffanson fails to disclose bonding the window cavity wafer (701/102) to the readout integrated circuit (optical readout of 1 on 111). However, it would have been obvious to one of ordinary skill in the art at the time the invention was made to bond the window cavity wafer to the readout integrated circuit since the selection of any order of performing process steps is prima facie obvious in the absence of new or unexpected results. In re Burhans, 154 F.2d 690, 69 USPQ 330 (CCPA 1946); In re Gibson, 39 F.2d 975, 5 USPQ 230 (CCPA 1930). See MPEP § 2144.04. Re claim 17, Steffanson discloses the method of claim 14, wherein the applied one or more optical coatings include one or more of an antireflective coating, an optical filter coating, and/or a long-pass blocker coating (see claim 2), as part of the method of forming the hermetically sealed window cavity wafer discussed for claim 14. Re claim 18, Steffanson and Huang disclose the method of claim 14, wherein: the provided window wafer substrate has a thickness between 300 µm and 1000 µm, and the provided window wafer substrate is one of: silicon (Si), germanium (Ge), borofloat glass, or sapphire (see claim 3); and/or the provided spacer wafer substrate has a thickness between 100 µm and 500 µm, and the provided spacer wafer substrate comprises one of: glass, sapphire, ceramic, or metal alloy (see claim 3), as part of the method of forming the hermetically sealed window cavity wafer discussed for claim 14. Re claim 20, Steffanson discloses the method of claim 14. But, fails to disclose the method further comprising: depositing a diamond-like carbon (DLC) coating over one of the optical coatings (unseen anti-reflection or filter layers; [0102]). However, Stark discloses a diamond-like carbon (DLC) coating (Diamonix; [0197]) over a surface of a window (314; [0197]). Thus, it would have been to deposit the diamond-like carbon (DLC) coating over one of the optical coatings, as claimed, to provide a scratch resistant/abrasion resistant material over the one of the optical coatings ([0197]). Re claim 21, Steffanson and Huang disclose the method of claim 15, wherein the deposited one or more metal layers comprise seed layer stacks, wherein the seed layer stacks comprise one of: (i) Cr + Ni + Au (see claim 7); or (ii) Ti + Pt + Au (see claim 7), as part of the method of forming the hermetically sealed window cavity wafer discussed for claim 14. Re claim 25, Steffanson and Huang disclose the method of claim 15, further comprising: depositing a metal plating layer over one of the metal layers (see claim 11), as part of the method of forming the hermetically sealed window cavity wafer discussed for claim 14. Re claim 26, Steffanson discloses the method of claim 14, further comprising: disposing a glass layer on one face of the spacer wafer substrate (see claim 12), as part of the method of forming the hermetically sealed window cavity wafer discussed for claim 14. Re claim 27, Steffanson discloses in FIGS. 20A-20B a method for forming a window cavity wafer (see claim 14), comprising: fabricating a window wafer (see claim 14) by: providing a window wafer substrate having two faces (see claim 14); polishing (double-sided; [0102]) one or more faces (upper/lower planes) of the window wafer substrate (701); and applying one or more optical coatings to on one or more faces of the window wafer substrate (see claim 14); fabricating a spacer wafer separate from the window wafer by (see claim 14): providing a spacer wafer substrate having two faces (see claim 14); and forming cavities on the faces of the spacer wafer substrate (see claim 14); bonding the spacer wafer to the window wafer to form the window cavity wafer (see claim 14). But, Steffanson fails to disclose etching one or more faces of the window wafer substrate (701); and forming discrete metal frames on a face of the window cavity wafer (701/102). However, A. Stark discloses a window cavity wafer method comprising: etching (PCM; [0243] and [0389]) one or more faces (exposed surfaces) of a window cavity wafer substrate (302 and 1722; [0243] and [0389]). And, B. Steffanson discloses in FIG. 10 a window cavity wafer comprising: eutectic bonds between substrates ([0073]). And, C. Huang discloses in FIG. 2 a window cavity wafer comprising: wherein a window cavity wafer (100) includes metal frames (110; [0036] and [0047]-[0048]) for bonds between wafers (laminate 106/108/110 and 112; [0036]). Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Steffanson by first applying the etching of the one or more faces of the window wafer substrate, of Park, to the window wafer substrate of Steffanson, facilitating separation of the window cavity wafer substrate bending instead of cutting (Stark; [0444]). And, then using the eutectic bonding concept of Steffanson with the metal frames of Huang between the window and spacer wafers of Steffanson, such that discrete metal frames are formed on a face of the window cavity wafer (700) for the predictable result(s) of a hermetically sealed (Steffanson: [0070] and Huang: [0047]) window cavity wafer. Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Steffanson and Huang as applied to claim 1 above, and further in view of Stark. Re claim 5, Steffanson and Huang disclose the window cavity wafer of claim 1. But, fail to disclose the window cavity wafer further comprising: a diamond-like carbon (DLC) coating disposed over one of the optical coatings. However, Stark renders these limitations (see claim 20 above). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIC W JONES whose telephone number is (408) 918-9765. The examiner can normally be reached M-F 7:00 AM - 6:00 PM PT. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, N. Drew Richards can be reached at (571) 272-1736. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ERIC W JONES/Primary Examiner, Art Unit 2892
Read full office action

Prosecution Timeline

Apr 04, 2024
Application Filed
Jun 18, 2026
Non-Final Rejection mailed — §102, §103 (current)

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Prosecution Projections

1-2
Expected OA Rounds
62%
Grant Probability
79%
With Interview (+17.3%)
3y 1m (~10m remaining)
Median Time to Grant
Low
PTA Risk
Based on 702 resolved cases by this examiner. Grant probability derived from career allowance rate.

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