DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 10 February 2026 is entered.
Response to Arguments
Applicant’s arguments have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
i. Claims 1 – 3, 7, 8, 10 – 13, 17, 18 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (2024/0321223; hereinafter Kim) and Wang et al. (2022/0189402; hereinafter Wang) in view of Cho et al. (2023/0335056; hereinafter Cho; this combination of references hereinafter referred to as KWC).
Regarding claim 1, Kim discloses a pixel driving circuit (Figure 3), comprising:
an initializing unit (Comprising T5), a data writing unit (Comprising T2), a light emitting control unit (Comprising T3, T4), a reset unit (Comprising T2, T6), a driving transistor (Comprising DRT) and a storage capacitor (Comprising Cst); wherein,
the initializing unit (Comprising T5) is configured to transmit an initialization voltage (Comprising Vini) to a second node (Shared with one electrode of Cst, gate of DRT, one of source and drain of T1) in response to an initialization scanning signal (Comprising SCAN3) to charge the storage capacitor (Comprising Cst);
the second node is a connection node among a second terminal of the storage capacitor (One electrode of Cst), a control terminal of the driving transistor (Comprising gate of DRT) and a threshold compensation unit (Comprising T1);
the threshold compensation unit (Comprising T1) is configured to obtain a threshold voltage ([0139], [0140]) of the driving transistor (Comprising DRT) in response to a first scanning signal scanned at a first frequency (Comprising SCAN1; see waveform frequency in Figure 5) and to update a potential of the second node ([0140]: DRT gate electrode – of which second node is comprised – is charged);
the data writing unit (Comprising T2) is configured to transmit a data signal (Comprising Vdata) to a first node (Intersecting current path formed between T3, DRT) in response to the first scanning signal or a second scanning signal (Comprising SCAN2);
the first node is a connection node between a first terminal of the driving transistor (Comprising one of source and drain of DRT) and the light emitting control unit (Comprising T3, T4);
the reset unit (Comprising T2, T6) is configured to reset a potential of the first node [0174] through a reset voltage (Comprising VOBS) in response to the second scanning signal scanned at a second frequency (Comprising SCAN2; see waveform frequency in Figure 5), and to change a forward bias state of an organic light emitting diode [0225], wherein the reset voltage (Comprising VOBS) is provided by a data line [0155] during a reset phase (Comprising a skip frame) that is not a data writing phase (Comprising sampling within a refresh frame); and
the light emitting control unit (Comprising T3, T4) is configured to transmit a driving current output by the driving transistor (Comprising DRT) to the organic light emitting diode (Comprising ED) in response to a light emitting control signal (Comprising EM) to cause the organic light emitting diode to emit light [0167]; wherein
the second frequency is N times the first frequency, and N is an integer greater than or equal to 1 (Figure 6: SCAN1, SCAN2 shown with approximately same frequency1), wherein the reset unit comprises a first transistor (Figure 3: Comprising T2) and a seventh transistor (Comprising T6), and the data writing unit comprises the first transistor (Comprising T2); wherein
a first terminal of the first transistor (Comprising one of source and drain of T2) is connected to the data line (Transmitting Vdata), a second terminal of the first transistor (Comprising other one of source and drain of T2) is connected to the first node (Intersecting current path formed between T3, DRT), and a control terminal of the first transistor (Comprising gate of T2) is connected to a second scanning line (Transmitting SCAN2); and wherein
a first terminal of the seventh transistor (Comprising one of source and drain of T6) is connected to an initialization signal terminal (Transmitting VAR), a second terminal of the seventh transistor (Comprising other one of source and drain of T6) is connected to an anode of the organic light emitting diode (Comprising ED).
Kim does not explicitly disclose the circuit wherein the reset unit is configured to reset a potential of the first node through a reset voltage and to change a forward bias state of an organic light emitting diode at the same time.
In the same field of endeavor, Wang discloses a pixel circuit [0002] wherein the reset unit (Comprising T7, T8) is configured to reset a potential of the first node (Comprising N1) through a reset voltage (VBIAS) and to change a forward bias state of an organic light emitting diode (Comprising ED) at the same time (By same bias control signal EB). This is among measures implemented to further reduce hysteresis and the resulting appearance of flicker within an image [0004].
It would be obvious to one having ordinary skill in the art before the filing date of the claimed invention for the circuit of Kim to be modified wherein the reset unit is configured to reset a potential of the first node through a reset voltage and to change a forward bias state of an organic light emitting diode at the same time, in view of the teaching of Wang, to reduce flicker.
Kim in view of Wang does not explicitly disclose the circuit wherein a control terminal of the seventh transistor is connected to the second scanning line.
In the same field of endeavor, Cho discloses display pixels [0002] wherein a control terminal of the first transistor (Figure 9: Comprising gate of M2) is connected to a second scanning line (Comprising S4i); and wherein a control terminal of the seventh transistor (Comprising gate of M8_1) is connected to the second scanning line (Comprising S4i). This is among measures by which luminance uniformity is restored [0006].
It would be obvious to one having ordinary skill in the art before the filing date of the claimed invention for the circuit of Kim to be modified wherein a control terminal of the seventh transistor is connected to the second scanning line, in view of the teaching of Cho, to restore luminance uniformity.
Regarding claim 2, KWC discloses the pixel driving circuit according to claim 1. Kim discloses the circuit (Figure 3) further comprising a first power supply (Comprising VDD) and a second power supply (Comprising VSS), wherein the light emitting control unit (Comprising T3, T4) is connected between the first power supply (Comprising VDD) and the second power supply (Comprising VSS), and a first terminal of the storage capacitor (Comprising one of two terminals of Cst) is connected to the first power supply (Comprising VDD); wherein the light emitting control unit comprises a fourth transistor (Comprising T3) and a fifth transistor (Comprising T4); wherein a first terminal of the fourth transistor (Comprising one of source and drain of T3) is connected to the first power supply (Comprising VDD), a second terminal of the fourth transistor (Comprising other one of source and drain of T3) is connected to the first node (Intersecting current path formed between T3, DRT), and a control terminal of the fourth transistor (Comprising gate of T3) is connected to an emitting control line (Transmitting EM); and a first terminal of the fifth transistor (Comprising one of source and drain of T4) is connected to a third node (Shared with one of source and drain of DRT, and one of source and drain of T1), a second terminal of the fifth transistor (Comprising other one of source and drain of T4) is connected to an anode of the organic light emitting diode (Comprising ED), and a control terminal of the fifth transistor (Comprising gate of T4) is connected to the emitting control line (Transmitting EM).
Regarding claim 3, KWC discloses the pixel driving circuit according to claim 1. Kim discloses the circuit (Figure 3) wherein the threshold compensation unit comprises a third transistor (Comprising T1), wherein a first terminal of the third transistor (Comprising one of source and drain of T1) is connected to the second node (Shared with gate of DRT, one of source and drain of T5, one electrode of Cst), a second terminal of the third transistor (Comprising other one of source and drain of T1) is connected to a third node (Shared with one of source and drain of DRT, one of source and drain of T4), and a control terminal of the third transistor (Comprising gate of T1) is connected to a first scanning line (Comprising SCAN1).
Regarding claim 7, KWC discloses the pixel driving circuit according to claim 1. Kim discloses the circuit (Figure 3) wherein the initializing unit comprises a sixth transistor (Comprising T5), a first terminal of the sixth transistor (Comprising one of source and drain of T5) is connected to the initialization signal terminal (Transmitting Vini), a second terminal of the sixth transistor (Comprising other one of source and drain of T5) is connected to the second node (Shared with one of two electrodes of Cst, gate of DRT, one of source and drain of T1), and a control terminal of the sixth transistor (Comprising gate of T5) is connected to a third scanning line (Transmitting SCAN3).
Regarding claim 8, KWC discloses the pixel driving circuit according to claim 1. Kim discloses the circuit (Figure 3) wherein the driving transistor is a second transistor (Comprising DRT), a first terminal of the second transistor (Comprising one of source and drain of DRT) is connected to the first node (Intersecting current path formed between T3, DRT), a second terminal of the second transistor (Comprising other one of source and drain of DRT) is connected to a third node (Shared with one of source and drain of T1, one of source and drain of T4), and a control terminal of the second transistor (Comprising gate of DRT) is connected to the second node (Shared with one electrode of Cst, one of source and drain of T5, one of source and drain of T1).
Method claim 10 is rejected as reciting limitations similar to those recited in circuit claim 1.
Apparatus claims 11 – 13, 17, 18 are rejected as reciting limitations similar to those recited in circuit claims 1 – 3, 7, 8 respectively.
ii. Claims 9, 19 are rejected under 35 U.S.C. 103 as being unpatentable over KWC as respectively applied to claims 1, 11 above, and further in view of Xu et al. (2024/0172508; hereinafter Xu).
Regarding claim 9, KWC discloses the pixel driving circuit according to claim 1. Kim discloses the circuit further (Figure 1) comprising a scanning circuit (Comprising 120).
KWC does not explicitly disclose the circuit wherein the scanning circuit comprises a cascaded first gate driver on array circuit, a cascaded second gate driver on array circuit, a cascaded third gate driver on array circuit, and a light emitting control signal driving circuit; wherein, the first gate driver on array circuit is configured to output the first scanning signal; the second gate driver on array circuit is configured to output the second scanning signal; the third gate driver on array circuit is configured to output a third scanning signal; and the light emitting control signal driving circuit is configured to output the light emitting control signal.
In the same field of endeavor, Xu discloses a display substrate [0002] wherein the scanning circuit comprises a cascaded [0141] first gate driver on array [0063] circuit (Comprising 231), a cascaded [0109] second gate driver on array [0063] circuit (Comprising 221), a cascaded [0109] third gate driver on array [0063] circuit (Comprising 222), and a light emitting control signal driving circuit (Comprising 211); wherein, the first gate driver on array circuit (Comprising 231) is configured to output the first scanning signal (Transmitted on e.g. GP1); the second gate driver on array circuit (Comprising 221) is configured to output the second scanning signal (Transmitted on e.g. GN1); the third gate driver on array circuit (Comprising 222) is configured to output a third scanning signal (Transmitted on e.g. RT1); and the light emitting control signal driving circuit (Comprising 211) is configured to output the light emitting control signal (Transmitted on e.g. E1). These are among measures implemented to reduce the varying delay times on GOA wiring at different locations [0063].
It would be obvious to one having ordinary skill in the art before the filing date of the claimed invention for the device of Kim to be modified wherein the scanning circuit comprises a cascaded first gate driver on array circuit, a cascaded second gate driver on array circuit, a cascaded third gate driver on array circuit, and a light emitting control signal driving circuit; wherein, the first gate driver on array circuit is configured to output the first scanning signal; the second gate driver on array circuit is configured to output the second scanning signal; the third gate driver on array circuit is configured to output a third scanning signal; and the light emitting control signal driving circuit is configured to output the light emitting control signal, in view of the teaching of Xu, to reduce the variance of signal delay times.
Apparatus claim 19 is rejected as reciting limitations similar to those recited in circuit claim 9.
Conclusion
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/AARON MIDKIFF/
Examiner, Art Unit 2621
/AMR A AWAD/Supervisory Patent Examiner, Art Unit 2621
1 Example wherein N = 1.