DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Applicant amended claims 3, 6, 7, 10, 13, and 14 on 4/10/2024.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 3, 6, 8, 10, and 13 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Manos et al. (US 2012/0080725) (hereafter Manos).
Regarding claim 1, Manos discloses a circuit arrangement comprising:
a plurality of two-terminal devices 214 (Fig. 14B, paragraph 0076, wherein “non-volatile variable resistive memory cell such as a STRAM or RRAM memory cell”);
a via interconnection circuit (205, 210, and 213 in Fig. 14B) comprising:
a support structure 205 (Fig. 14B, paragraph 0079);
a plurality of through-vias 210 (Fig. 14B, paragraph 0079) defined through the support structure 205 (Fig. 14B); and
a plurality of via trenches (region where 213 is formed in Fig. 14B) defined in the support structure 205 (Fig. 14B), the plurality of via trenches (region where 213 is formed in Fig. 14B) being arranged to allow electrical coupling to the plurality of through-vias 210 (Fig. 14B); and
a selection circuit 112 (Fig. 14B, paragraph 0047, wherein “switching device”) comprising a plurality of selection devices 112 (Fig. 14B), wherein, for each two-terminal device 214 (Fig. 14B) of the plurality of two-terminal devices, the two-terminal device 214 (Fig. 14B) is arranged outside of a respective via trench of the plurality of via trenches (region where 213 is formed in Fig. 14B), the two-terminal device 214 (Fig. 14B) being electrically coupled to a respective selection device 112 (Fig. 14B) of the plurality of selection devices in a one-to-one arrangement through the respective via trench (region where 213 is formed in Fig. 14B) and a respective through-via 210 (Fig. 14B) of the plurality of through-vias.
Regarding claim 3, Manos further discloses the circuit arrangement as claimed in claim 1, wherein the two-terminal device 214 (Fig. 14B, paragraph 0076, wherein “non-volatile variable resistive memory cell such as a STRAM or RRAM memory cell”) comprises a memory device.
Regarding claim 6, Manos further discloses the circuit arrangement as claimed in claim 1, wherein each selection device 112 (Fig. 14B, paragraph 0047, wherein “n-channel MOSFETs (transistors)”) of the plurality of selection devices comprises a transistor.
Regarding claim 8, Manos discloses a method of forming a circuit arrangement comprising:
forming a plurality of two-terminal devices 214 (Fig. 14B, paragraph 0076, wherein “non-volatile variable resistive memory cell such as a STRAM or RRAM memory cell”) on a via interconnection circuit (205, 210, and 213 in Fig. 14B) of the circuit arrangement, the via interconnection circuit (205, 210, and 213 in Fig. 14B) comprising:
a support structure 205 (Fig. 14B, paragraph 0079);
a plurality of through-vias 210 (Fig. 14B, paragraph 0079) defined through the support structure 205 (Fig. 14B); and
a plurality of via trenches (region where 213 is formed in Fig. 14B) defined in the support structure 205 (Fig. 14B), the plurality of via trenches (region where 213 is formed in Fig. 14B) being arranged to allow electrical coupling to the plurality of through-vias 210 (Fig. 14B); and
electrically coupling the plurality of two-terminal devices 214 (Fig. 14B) to a selection circuit 112 (Fig. 14B, paragraph 0047, wherein “switching device”) of the circuit arrangement, the selection circuit 112 (Fig. 14B) comprising a plurality of selection devices 112 (Fig. 14B), wherein, for each two-terminal device 214 (Fig. 14B) of the plurality of two-terminal devices, the two-terminal device 214 (Fig. 14B) is arranged outside of a respective via trench (region where 213 is formed in Fig. 14B) of the plurality of via trenches, the two-terminal device 214 (Fig. 14B) being electrically coupled to a respective selection device 112 (Fig. 14B) of the plurality of selection devices in a one-to-one arrangement through the respective via trench (region where 213 is formed in Fig. 14B) and a respective through-via of the plurality of through-vias 210 (Fig. 14B).
Regarding claim 10, Manos further discloses the method as claimed in claim 8, wherein the two-terminal device 214 (Fig. 14B, paragraph 0076, wherein “non-volatile variable resistive memory cell such as a STRAM or RRAM memory cell”) comprises a memory device.
Regarding claim 13, Manos further discloses the method as claimed in claim 8, wherein each selection device 112 (Fig. 14B, paragraph 0047, wherein “n-channel MOSFETs (transistors)”) of the plurality of selection devices comprises a transistor.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 2, 4, 5, 7, 9, 11, 12, and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Manos as applied to claims 1, 3, and 8 above, and further in view of Chiu et al. (US 2021/0111339) (hereafter Chiu).
Regarding claim 2, Manos discloses the circuit arrangement as claimed in claim 1, however Manos does not disclose the via interconnection circuit further comprises:
at least one metal line electrically coupled to the plurality of through-vias, wherein the plurality of via trenches are arranged to allow electrical coupling to the at least one metal line,
wherein the two-terminal device is electrically coupled to the respective selection device through the respective via trench, the respective through-via and the at least one metal line.
Chiu discloses the via interconnection circuit (106a, 107a, 106b, 107b, 106c, 110, 210, 202, 204, 206 in Fig. 2) further comprises:
at least one metal line 206 (Fig. 2, paragraph 0028) electrically coupled to the plurality of through-vias 202 (Fig. 2, paragraph 0028), wherein the plurality of via trenches (region where 204 is formed Fig. 2, paragraph 0028) are arranged to allow electrical coupling to the at least one metal line 206 (Fig. 2),
wherein the two-terminal device 112 (Fig. 2, paragraph 0021) is electrically coupled to the respective selection device 104 (Fig. 2, paragraph 0062) through the respective via trench (region where 204 is formed Fig. 2), the respective through-via 202 (Fig. 2) and the at least one metal line 206 (Fig. 2).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Manos to form the via interconnection circuit further comprises: at least one metal line electrically coupled to the plurality of through-vias, wherein the plurality of via trenches are arranged to allow electrical coupling to the at least one metal line, wherein the two-terminal device is electrically coupled to the respective selection device through the respective via trench, the respective through-via and the at least one metal line, as taught by Chiu, since at least one metal line 206 (Chiu, Fig. 2, paragraph 0028) provides electrical connection between the two-terminal device 112 (Chiu, Fig. 2, paragraph 0021) and the selection device 104 (Chiu, Fig. 2, paragraph 0062).
Regarding claim 4, Manos discloses the circuit arrangement as claimed in claim 3, however Manos does not disclose the memory device comprises:
a first electrode;
a second electrode; and
a resistive switching material in between the first electrode and the second electrode.
Chiu discloses the memory device 112 (Fig. 2, paragraph 0021) comprises:
a first electrode 126a (Fig. 2, paragraph 0024);
a second electrode 126b (Fig. 2, paragraph 0024); and
a resistive switching material 116 (Fig. 2, paragraph 0023) in between the first electrode 126a (Fig. 2) and the second electrode 126b (Fig. 2).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Manos to form the memory device comprises: a first electrode; a second electrode; and a resistive switching material in between the first electrode and the second electrode, as taught by Chiu, since the resistive switching material/data storage structure 116 (Chiu, Fig. 2, paragraph 0023) is configured to store different data states by undergoing reversible changes between a high resistive state associated with a first data state (e.g., a ‘0’) and a low resistive state associated with a second data state (e.g., a ‘1’).
Regarding claim 5, Manos in view of Chiu discloses the circuit arrangement as claimed in claim 4, however Manos does not disclose the memory device further comprises a protective layer in between the resistive switching material and one of the first and second electrodes.
Chiu discloses the memory device 112 (Fig. 2, paragraph 0021) further comprises a protective layer 210 (Fig. 2, paragraph 0035) in between the resistive switching material 116 (Fig. 2) and one of the first and second electrodes 126b (Fig. 2).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Manos to form the memory device further comprises a protective layer in between the resistive switching material and one of the first and second electrodes, as taught by Chiu, since a protective layer 210 (Chiu, Fig. 2, paragraph 0035) protects underneath layers.
Regarding claim 7, Manos discloses the circuit arrangement as claimed in claim 1, however Manos does not disclose the support structure comprises a shielding layer, wherein the plurality of via trenches are defined through the shielding layer.
Chiu discloses the support structure (106a, 107a, 106b, 107b, 106c, 110, and 210 in Fig. 2) comprises a shielding layer 107a (Fig. 2, paragraph 0069, wherein “first etch stop layer”), wherein the plurality of via trenches 204 (Fig. 2, paragraph 0028) are defined through the shielding layer 107a (Fig. 2).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Manos to form the support structure comprises a shielding layer, wherein the plurality of via trenches are defined through the shielding layer, as taught by Chiu, since a shielding layer/etch stop layer 107a (Chiu, Fig. 2, paragraph 0069) protects the lower ILD layer 106a (Chiu, Fig. 2, paragraph 0069).
Regarding claim 9, Manos discloses the method as claimed in claim 8, however Manos does not disclose the via interconnection circuit further comprises:
at least one metal line electrically coupled to the plurality of through-vias, wherein the plurality of via trenches are arranged to allow electrical coupling to the at least one metal line,
wherein the two-terminal device is electrically coupled to the respective selection device through the respective via trench, the respective through-via and the at least one metal line.
Chiu discloses the via interconnection circuit (106a, 107a, 106b, 107b, 106c, 110, 210, 202, 204, 206 in Fig. 2) further comprises:
at least one metal line 206 (Fig. 2, paragraph 0028) electrically coupled to the plurality of through-vias 202 (Fig. 2, paragraph 0028), wherein the plurality of via trenches (region where 204 is formed Fig. 2, paragraph 0028) are arranged to allow electrical coupling to the at least one metal line 206 (Fig. 2),
wherein the two-terminal device 112 (Fig. 2, paragraph 0021) is electrically coupled to the respective selection device 104 (Fig. 2, paragraph 0062) through the respective via trench (region where 204 is formed Fig. 2), the respective through-via 202 (Fig. 2) and the at least one metal line 206 (Fig. 2).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Manos to form the via interconnection circuit further comprises: at least one metal line electrically coupled to the plurality of through-vias, wherein the plurality of via trenches are arranged to allow electrical coupling to the at least one metal line, wherein the two-terminal device is electrically coupled to the respective selection device through the respective via trench, the respective through-via and the at least one metal line, as taught by Chiu, since at least one metal line 206 (Chiu, Fig. 2, paragraph 0028) provides electrical connection between the two-terminal device 112 (Chiu, Fig. 2, paragraph 0021) and the selection device 104 (Chiu, Fig. 2, paragraph 0062).
Regarding claim 11, Manos discloses the method as claimed in claim 10, however Manos does not disclose the memory device comprises:
a first electrode;
a second electrode; and
a resistive switching material in between the first electrode and the second electrode.
Chiu discloses the memory device 112 (Fig. 2, paragraph 0021) comprises:
a first electrode 126a (Fig. 2, paragraph 0024);
a second electrode 126b (Fig. 2, paragraph 0024); and
a resistive switching material 116 (Fig. 2, paragraph 0023) in between the first electrode 126a (Fig. 2) and the second electrode 126b (Fig. 2).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Manos to form the memory device comprises: a first electrode; a second electrode; and a resistive switching material in between the first electrode and the second electrode, as taught by Chiu, since the resistive switching material/data storage structure 116 (Chiu, Fig. 2, paragraph 0023) is configured to store different data states by undergoing reversible changes between a high resistive state associated with a first data state (e.g., a ‘0’) and a low resistive state associated with a second data state (e.g., a ‘1’).
Regarding claim 12, Manos in view of Chiu discloses the method as claimed in claim 11, however Manos does not disclose the memory device further comprises a protective layer in between the resistive switching material and one of the first and second electrodes.
Chiu discloses the memory device 112 (Fig. 2, paragraph 0021) further comprises a protective layer 210 (Fig. 2, paragraph 0035) in between the resistive switching material 116 (Fig. 2) and one of the first and second electrodes 126b (Fig. 2).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Manos to form the memory device further comprises a protective layer in between the resistive switching material and one of the first and second electrodes, as taught by Chiu, since a protective layer 210 (Chiu, Fig. 2, paragraph 0035) protects underneath layers.
Regarding claim 14, Manos discloses the method as claimed in claim 8, however Manos does not disclose the support structure comprises a shielding layer, wherein the plurality of via trenches are defined through the shielding layer.
Chiu discloses the support structure (106a, 107a, 106b, 107b, 106c, 110, and 210 in Fig. 2) comprises a shielding layer 107a (Fig. 2, paragraph 0069, wherein “first etch stop layer”), wherein the plurality of via trenches 204 (Fig. 2, paragraph 0028) are defined through the shielding layer 107a (Fig. 2).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Manos to form the support structure comprises a shielding layer, wherein the plurality of via trenches are defined through the shielding layer, as taught by Chiu, since a shielding layer/etch stop layer 107a (Chiu, Fig. 2, paragraph 0069) protects the lower ILD layer 106a (Chiu, Fig. 2, paragraph 0069).
Conclusion
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/L.B.K/Examiner, Art Unit 2813
/STEVEN B GAUTHIER/Supervisory Patent Examiner, Art Unit 2813
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