Prosecution Insights
Last updated: August 17, 2026
Application No. 18/700,127

SEMICONDUCTOR DEVICE, SOLID-STATE IMAGING DEVICE, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

Non-Final OA §102§103
Filed
Apr 10, 2024
Priority
Oct 18, 2021 — JP 2021-170226 +1 more
Examiner
LEE, EUGENE
Art Unit
Tech Center
Assignee
Sony Group Corporation
OA Round
1 (Non-Final)
82%
Grant Probability
Favorable
1-2
OA Rounds
3m
Est. Remaining
88%
With Interview

Examiner Intelligence

Grants 82% — above average
82%
Career Allowance Rate
748 granted / 914 resolved
+21.8% vs TC avg
Moderate +6% lift
Without
With
+5.7%
Interview Lift
resolved cases with interview
Typical timeline
2y 8m
Avg Prosecution
41 currently pending
Career history
947
Total Applications
across all art units

Statute-Specific Performance

§101
0.5%
-39.5% vs TC avg
§103
59.9%
+19.9% vs TC avg
§102
16.5%
-23.5% vs TC avg
§112
13.3%
-26.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 914 resolved cases

Office Action

§102 §103
DETAILED ACTION Election/Restrictions Applicant’s election without traverse of Group I, FIG. 1A-11 (claims 1-4, 7-13, and 15-21) in the reply filed on is acknowledged. Claims 5, 6, 14, and 22-30 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 7/8/26. Drawings The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they include the following reference character(s) not mentioned in the description: 153d. See Fig. 11. Corrected drawing sheets in compliance with 37 CFR 1.121(d), or amendment to the specification to add the reference character(s) in the description in compliance with 37 CFR 1.121(b) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance. The drawings are objected to because the Drawings are grainy, lacking resolution that it is difficult to determine where certain elements are pointing to. For example, in Fig. 1B, element 300 and element 100b appear to be pointing to the same structure. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance. The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the another substrate including a pixel part (claim 21) must be shown or the feature(s) canceled from the claim(s). No new matter should be entered. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance. Claim Objections Claim 4 is objected to because of the following informalities: in line 1, the limitation “wherein element part” appears to contain a typographical error. Appropriate correction is required. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1 thru 4, 7 thru 12, and 15 thru 19 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Jeon et al. US 2017/0103916 A1. Jeon discloses (see, for example, FIG. 2) a semiconductor device comprising a semiconductor device comprising: a substrate 100; and at least one element part 140/130/120/125 provided on the substrate 100, wherein at least a part of the element part 141 is shaped to increase in width toward the substrate, the part including a side 142 opposite to a side near the substrate 100. Regarding claim 2, see, for example, FIG. 2 wherein Jeon discloses an embedded layer 181. Regarding claims 3, see, for example, paragraph [0119] wherein Jeon discloses a part 141 of the element part 140 is shaped to increase in width toward the substrate 100, the part 141 including the side 142 opposite to the side near the substrate 100. Regarding claim 4, see, for example, FIG. 2 wherein Jeon discloses element part 140 is entirely shaped to increase in width toward the substrate. Regarding claim 7, see, for example, FIG. 2 wherein Jeon discloses a protective film 130. Regarding claim 8, see, for example, FIG. 2 wherein Jeon discloses a wiring layer MG1, semiconductor layer MG2, and side wall 140. In paragraph [0087], Jeon discloses the semiconductor layer MG2 includes poly-Si, etc. Regarding claim 9, see, for example, FIG. 2 wherein Jeon discloses the side wall 140 being part of a protective film covering the semiconductor layer MG2, the wiring layer MG1 and the substrate 100. Regarding claim 10, see, for example, FIG. 2 wherein Jeon discloses a protective film 127. Regarding claims 11-12, see, for example, paragraph [0023] wherein Jeon discloses the side wall 140 may include SiOCN, which is an inorganic material, and type of SiN material. Regarding claim 15, see, for example, paragraph [0109] wherein Jeon discloses includes silicon oxide, etc. which are inorganic materials. Regarding claim 16, see, for example, FIG. 2 wherein Jeon discloses a semiconductor substrate 100 and wiring layer MG1. Regarding claim 17, see, for example, FIG. 2 wherein Jeon discloses at least one element part 140t being a plurality of element parts 140t/240t. Regarding claims 18-19, see, for example, paragraph [0046] wherein Jeon discloses a memory element, etc. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jeon et al. US 2017/0103916 A1, as applied to claims 1-4, 7-12, and 15-19. Jeon does not specifically disclose the widest part of the side wall has a width of 450 nm or more in an in-plane direction. However, it would have been obvious to one of ordinary skill in the art, at a time prior to the effective filing date, to have the widest part of the side wall has a width of 450 nm or more in an in-plane direction in order to increase operating speed while enhancing integration, since it has been held that discovering the optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F. 2d 272, 205 USPQ 215 (CCPA 1980). Claim(s) 20, and 21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jeon et al. US 2017/0103916 A1, as applied to claims 1-4, 7-12, and 15-19, and further in view of WO 2020/129712 A1. Jeon does not disclose the pixel part having a photoelectric conversion element, and each of the element part processes a signal outputted from the substrate. However, WO 2020/129712 A1 discloses (see, for example, figure 18) a semiconductor device 1 comprising a pixel part having photoelectric conversion element 41 and each of the element part processes a signal outputted from the substrate. It would have been obvious to one of ordinary skill in the art, at a time prior to the effective filing date, to have the pixel part having a photoelectric conversion element, and each of the element part processes a signal outputted from the substrate in order to utilize the semiconductor device into a more robust circuit such as an imager and/or display device. Regarding claim 21, see, for example, figure 1 wherein WO 2020/129712 A1 discloses another substrate 11. INFORMATION ON HOW TO CONTACT THE USPTO Any inquiry concerning this communication or earlier communications from the examiner should be directed to EUGENE LEE whose telephone number is (571)272-1733. The examiner can normally be reached M-F 730-330 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, JOSHUA BENITEZ can be reached at 571-270-1435. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. Eugene Lee July 15, 2026 /EUGENE LEE/Primary Examiner, Art Unit 2815
Read full office action

Prosecution Timeline

Apr 10, 2024
Application Filed
Jul 23, 2026
Non-Final Rejection mailed — §102, §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

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DISPLAY PANEL AND DISPLAY DEVICE INCLUDING THE SAME
3y 6m to grant Granted Aug 04, 2026
Patent 12690227
SEMICONDUCTOR DEVICE
2y 8m to grant Granted Jul 21, 2026
Patent 12684826
AVALANCHE-PROTECTED TRANSISTORS USING A BOTTOM BREAKDOWN CURRENT PATH AND METHODS OF FORMING THE SAME
3y 12m to grant Granted Jul 14, 2026
Patent 12677650
SEMICONDUCTOR STRUCTURES AND METHOD FOR MANUFACTURING A SEMICONDUCTOR STRUCTURE
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Patent 12666995
PACKAGE STRUCTURE
2y 10m to grant Granted Jun 23, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
82%
Grant Probability
88%
With Interview (+5.7%)
2y 8m (~3m remaining)
Median Time to Grant
Low
PTA Risk
Based on 914 resolved cases by this examiner. Grant probability derived from career allowance rate.

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