DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Applicant’s response filed on 08/20/2026 in which claim 1 is amended, claims 2, 3, 5-20 are withdrawn have been entered of record.
Election/Restrictions
Applicant's election with traverse of Species I(A)(1): Fig. 3 in the reply filed on 08/20/2020 is acknowledged. The traversal is on the ground(s) that claims 2-3 should be belong to Species I (A)(a). This is not found persuasive because:
The original election was for Group (I)(A)(1), Figure 3, which illustrates separate RBL and separate WBL with a read transistor's gate is connected to write transistor's source.
Applicant asserts claims 2 and 3 should be examined, because they allegedly read on elected Figure 3.This is not persuasive, because claim 2 recites the first electrode (connected to the RBL) and the sixth electrode (WBL) share one electrode, which is a mutually exclusive feature compared to Figure 3's separate RBL and a separate WBL. Claim 3 depends on claim 2, requiring this mutually exclusive shared RBL/WBL. This was fully explained in the Non-Final rejection, pages 2 to 4, which mailed on 05/28/2026.
The requirement is still deemed proper and is therefore made FINAL.
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Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 4 are rejected under 35 U.S.C. 103 as being unpatentable over Shionoiri et al. (US Pub. 9,472,559) in view of Tomishima (US Pub. 2021/0151437) and further in view of Tanioku Masami (JPH 07176184).
Regarding claim 1A, Fig. 1A of Shionoiri discloses a storage cell, comprising:
a first transistor [101], configured as a read transistor [101 output data Dout, and thus it is a read transistor]; and,
a second transistor [102, transistor 102 takes input data, and thus it is a write transistor], configured as a write transistor;
wherein, the first transistor [101] comprises a first electrode [T1], a second electrode [T2], a third electrode [T3] and a fourth electrode [T4]; the third electrode is a first gate, and the fourth electrode is a second gate [back gate];
the second transistor [102] comprises a fifth electrode [T5], a sixth electrode [T6] and a seventh electrode [T7]; the seventh electrode is a third gate;
the first electrode [T1] is configured to be connected to a read bit-line [Dout], the second electrode [T2] is configured to be connected to a reference signal [ground], the first gate is configured to be connected to a read word-line [RL], and the second gate [T4] is configured to be connected to the fifth electrode [T5];
the sixth electrode [T6] is configured to be connected to a write bit-line [Din], and the third gate [T7] is configured to be connected to a write word-line [WL];
Shionoiri discloses all claimed invention, but does not specifically disclose wherein both the first transistor and the second transistor are N-type transistors, and both the first transistor and the second transistor are indium gallium zinc oxide (IGZO) transistors. However, Fig. 4 of Tomishima shows a 2T memory cells wherein both the first transistor [430] and the second transistor [440] are N-type transistors, and both the first transistor and the second transistor are indium gallium zinc oxide (IGZO) transistors [IGZO transistor (BE), paragraph 0020].
Shionoiri in view of Tomishima discloses all claimed invention, but does not specifically disclose a storage cell having a 2T0c structure. However, Fig. 1 of Tanioku discloses a storage cell having a 2T0c structure [Q1 & Q2].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply the teachings of Tomishima’s 2T cells having IGZO transistors and Tanioku 2T0c structure hto the teachings of Shionoiri’s 2T memory cell such that Shionoiri’s 2T memory operate in a manner according to Tomishima’s teachings for the purpose of having low leakage current and higher operating rate [paragraph 0020].
Regarding claim 4, Fig. 1A of Shionoiri discloses wherein the first gate [T3] and the second gate [T4] are gates independent of each other, and the first gate is configured to control a read operation [controls by read word line WL] of the read transistor [101]; the second gate is configured to write an electrical signal to a storage node [103] through the write transistor [102] as the storage node of the storage cell.
Response to Arguments
Applicant’s arguments with respect to claim 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANTHAN T TRAN whose telephone number is (571)272-8709. The examiner can normally be reached MON-FRI, 9AM-5:00PM.
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/ANTHAN TRAN/Primary Examiner, Art Unit 2825
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