DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of Species I(A)(1): Figure 3, as indicated by applicant as corresponding to claims 1-4 and 19-20 in the reply filed on 04/23/2026 is acknowledged. The traversal is on the ground(s) that claim one comprises “special technical feature” and therefore there is no lack of unity. This is not found persuasive because:
Applicant asserts their election is "with traverse"; however, because applicant did not point out actual supposed errors the requirement based on lack of unity of invention mailed 3/6/26, this election is deemed without traverse. MPEP 818.01(a).
For purpose of completeness, applicant amended claim 1 to now require both transistors to be IGZO, and according to applicant, this is the "special technical feature" and therefore there is no lack of unity now (Remarks 2).
This argument is not a traversal of the requirement to elect based upon a presented lack of unity of invention mailed 3/6/26. The claims, as presented prior to instant amendment, had lack of unity at presentation. Applicant's amendment does not retroactively create a unity of invention, where unity of invention did not exist at the time the lack of unity was determined. As such, applicant's argument is incomplete as it does not satisfy the requirement to "distinctly and specifically point[] out the supposed errors in the examiner’s action" (i.e., the requirement to elect, based upon lack of unity, mailed 3/6/26), and therefore is not deemed a "traversal." MPEP 818.01(a).
Furthermore, to the extent applicant asserts that IGZO transistors are a "special technical feature" to thereby now bring unity of invention, IGZO transistors are not "special" and not inventive. Although Mitsubishi (the record evidence of a posteriori a lack of unity) does not disclose IGZO transistors, IGZO transistors are well-known in the art, especially as commonly disclosed feature of memory devices and other semiconductor devices disclosed by Semiconductor Energy Labs, well before applicant's effective filing date. For example, see Tomishima (US Pub. 2021/0151437), Fig. 4 and paragraph 0020.
Claims 5-18 are withdrawn from consideration. Because claim 19 depends from withdrawn claim 5, claim 19 is withdrawn from consideration. Because claim 20 depends from withdrawn claim 7, claim 20 is withdrawn from consideration.
Of the remaining claims applicant asserts are directed to Figure 3, not all of claims 1-4 are directed to Figure 3.
Claim 2 recites the "first electrode" and "sixth electrode" share one electrode. Antecedent claim 1 indicates the "first electrode" is a component of the "first transistor" (also claimed as the "read transistor") and is also "configured to be connected to a read bit-line." This "first electrode" illustrated in Figure 3 reflects R-BL connection to Tr_r. Antecedent claim 1 indicates the "sixth electrode" is a component of the "second transistor" (also claimed as the "write transistor") and is also "configured to be connected to a write bit-line." This "sixth electrode" illustrated in Figure 3 reflects W-BL connected to Tr_w. Because, in Figure 3, R-BL and W-BL do not "share one electrode" as required by claim 2. As such claim 2 is not directed to elected Group I(A)(1): Figure 3. Claim 2 is therefore withdrawn from consideration.
Because claim 3 depends from withdrawn claim 2, claim 3 is withdrawn from consideration.
Claim 4 is directed to Figure 3, as reciting features of the read transistor illustrated in Figure 3 as G1 and G2 (or alternately P3 and P4/P5).
Claims 1 and 4 are directed to the elected Group I(A)(1).
The requirement is still deemed proper and is therefore made FINAL.
PNG
media_image1.png
383
370
media_image1.png
Greyscale
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 4 are rejected under 35 U.S.C. 103 as being unpatentable over Shionoiri et al. (US Pub. 9,472,559) in view of Tomishima (US Pub. 2021/0151437).
Regarding claim 1A, Fig. 1A of Shionoiri discloses a storage cell, comprising:
a first transistor [101], configured as a read transistor [101 output data Dout, and thus it is a read transistor]; and,
a second transistor [102, transistor 102 takes input data, and thus it is a write transistor], configured as a write transistor;
wherein, the first transistor [101] comprises a first electrode [T1], a second electrode [T2], a third electrode [T3] and a fourth electrode [T4]; the third electrode is a first gate, and the fourth electrode is a second gate [back gate];
the second transistor [102] comprises a fifth electrode [T5], a sixth electrode [T6] and a seventh electrode [T7]; the seventh electrode is a third gate;
the first electrode [T1] is configured to be connected to a read bit-line [Dout], the second electrode [T2] is configured to be connected to a reference signal [ground], the first gate is configured to be connected to a read word-line [RL], and the second gate [T4] is configured to be connected to the fifth electrode [T5];
the sixth electrode [T6] is configured to be connected to a write bit-line [Din], and the third gate [T7] is configured to be connected to a write word-line [WL];
Shionoiri discloses all claimed invention, but does not specifically disclose wherein both the first transistor and the second transistor are N-type transistors, and both the first transistor and the second transistor are indium gallium zinc oxide (IGZO) transistors. However, Fig. 4 of Tomishima shows a 2T memory cells wherein both the first transistor [430] and the second transistor [440] are N-type transistors, and both the first transistor and the second transistor are indium gallium zinc oxide (IGZO) transistors [IGZO transistor (BE), paragraph 0020].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply the teachings of Tomishima’s 2T cells having IGZO transistors to the teachings of Shionoiri’s 2T memory cell such that Shionoiri’s 2T memory operate in a manner according to Tomishima’s teachings for the purpose of having low leakage current and higher operating rate [paragraph 0020].
Regarding claim 4, Fig. 1A of Shionoiri discloses wherein the first gate [T3] and the second gate [T4] are gates independent of each other, and the first gate is configured to control a read operation [controls by read word line WL] of the read transistor [101]; the second gate is configured to write an electrical signal to a storage node [103] through the write transistor [102] as the storage node of the storage cell.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANTHAN T TRAN whose telephone number is (571)272-8709. The examiner can normally be reached MON-FRI, 9AM-5:00PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Alexander G Sofocleous can be reached at 571-272-0635. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ANTHAN TRAN/Primary Examiner, Art Unit 2825
Prosecution Insights