Prosecution Insights
Last updated: July 17, 2026
Application No. 18/700,731

Organic Light-Emitting Transistor, Manufacturing Method thereof, Light Emitting Substrate, and Display Apparatus

Non-Final OA §102§112
Filed
Apr 12, 2024
Priority
May 30, 2022 — CN 202210605278.6 +1 more
Examiner
CHAMBLISS, ALONZO
Art Unit
Tech Center
Assignee
BOE Technology Group Co., Ltd.
OA Round
1 (Non-Final)
90%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
65%
With Interview

Examiner Intelligence

Grants 90% — above average
90%
Career Allowance Rate
1068 granted / 1186 resolved
+30.1% vs TC avg
Minimal -25% lift
Without
With
+-24.7%
Interview Lift
resolved cases with interview
Fast prosecutor
2y 1m
Avg Prosecution
23 currently pending
Career history
1208
Total Applications
across all art units

Statute-Specific Performance

§101
3.9%
-36.1% vs TC avg
§103
52.3%
+12.3% vs TC avg
§102
12.8%
-27.2% vs TC avg
§112
9.1%
-30.9% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1186 resolved cases

Office Action

§102 §112
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Priority Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55. Information Disclosure Statement The information disclosure statement (IDS) submitted on 10/10/2024 was filed before the mailing date of the Non-final rejection on June 25/2026. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. Drawings The formal drawings filed on 4/12/2024 have been approved by the examiner. Specification The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. The following title is suggested: “ ORGANIC LIGHT EMITTING TRANSISTOR ”. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 2, 16, and 18 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. With respect to Claim 2, the phrase “ an overlapping area S between an orthographic projection of the drain electrode on the substrate and an orthographic projection of the source electrode on the substrate is less than or equal to a product of an area SDrain of the drain electrode and a preset ratio k ” is vague and indefinite since it is not clear the claim what applicant is trying to make claim to for the drain electrode and source electrode. Also, what is the preset ratio k? Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1, 2, 11-13, and 18, insofar as being definite are rejected under 35 U.S.C. 102(a)(1) as being clearly anticipated by Choi et al. (US 2009/0008628). With respect to Claims 1 and 11-13, Choi teaches a gate 2, a gate insulation layer 3, a source electrode 4, a light emitting functional layer 6-8, and a drain electrode 5 which are disposed on a substrate 1. A side surface of the source electrode 4 towards the light emitting functional layer 6-8 is in contact with the light emitting functional layer 6-8 (see paragraphs 31-35 and 42-57; Figs. 1-10). With respect to Claims 2 and 18, Choi teaches a plurality of organic light emitting transistors with respect to the source electrode 2, the drain electrode 5 is disposed on a side of the light emitting functional layer 6-8 away from the substrate 1. An overlapping area S (i.e. a portion of the source electrode) between an orthographic projection of the drain electrode on the substrate and an orthographic projection (i.e. vertically extending from gate insulation layer 3) of the source electrode on the substrate is less than or equal to a product of an area SDrain (i.e. the combination of source / drain) of the drain electrode and a preset ratio k (see paragraph 70; Figs. 1-6). Allowable Subject Matter 10. Claims 3-17, 19, and 20 would be allowable if rewritten or amended to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action. The following is a statement of reasons for the indication of allowance subject matter: none of the prior art of record teaches or suggest the combination of a plurality of electrically-conductive formations on the first surface of the electrically- insulating substrate. Package molding material molded onto the at least one semiconductor die mounted to the die pad at said first surface of the electrically- insulating substrate, onto the plurality of electrically-conductive leads of the leadframe and onto the plurality of electrically-conductive formations to form a flat, no-leads package leaving the second surface of said electrically- insulating substrate uncovered by said package molding material and leaving bottom surfaces of the plurality of electrically-conductive leads uncovered by said package molding material. in claim 1. A surface of the source electrode towards the light emitting functional layer has a slope in claims 3 and 16. The gate insulation layer is disposed between the source electrode and the gate. The gate insulation layer comprises a side surface perpendicular to the substrate. The side surface is disposed around a periphery of the light emitting functional layer in claim 4. The forming the source, the gate insulation layer, the gate, the light emitting functional layer, and the drain electrode on the substrate comprises forming the source electrode and the gate insulation layer on the substrate. The source electrode and the gate insulation layer form a hollow structure; and forming the light emitting functional layer in the hollow structure in claim 14. The prior art made of record and not relied upon is cited primarily to show the product of the instant invention. Conclusion 11. Any inquiry concerning the communication or earlier communications from the examiner should be directed to Alonzo Chambliss whose telephone number is (571) 272-1927. If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Jacob Y. Choi can be reached on (469) 295-9060. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system Status information for published applications may be obtained from either Private PMR or Public PMR. Status information for unpublished applications is available through Private PMR only. For more information about the PMR system see hittp://pair-dkect.usptol gov. Should you have questions on access to the Private PMR system contact the Electronic Center (EBC) at 866-217-9197 (toll-free). AC/June 25, 2026 /Alonzo Chambliss/ Primary Examiner, Art Unit 2897
Read full office action

Prosecution Timeline

Apr 12, 2024
Application Filed
Jun 29, 2026
Non-Final Rejection mailed — §102, §112 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12685212
SWITCHING DEVICE ELECTRICALLY CONNECTED TO A LEAD FRAME BY A BONDING MATERIAL
3y 1m to grant Granted Jul 14, 2026
Patent 12672292
SEMICONDUCTOR DEVICE INCLUDING A PLURALITY OF DIELECTRIC LAYERS STACKED ON FERROELECTRIC LAYER
4y 1m to grant Granted Jun 30, 2026
Patent 12672553
ELECTRONIC PACKAGE AND MANUFACTURING METHOD THEREOF
2y 11m to grant Granted Jun 30, 2026
Patent 12672435
DISPLAY PANEL
2y 6m to grant Granted Jun 30, 2026
Patent 12666546
CIRCUIT BOARD WITH A PLURALITY OF LAMINATED INSULATING LAYERS HAVING CONDUCTIVE PASTE FILLED VIAS AND MANUFACTURING METHOD THEREOF
3y 7m to grant Granted Jun 23, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
90%
Grant Probability
65%
With Interview (-24.7%)
2y 1m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1186 resolved cases by this examiner. Grant probability derived from career allowance rate.

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