Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Prior Art of Record
The applicant's attention is directed to additional pertinent prior art cited in the accompanying PTO-892 Notice of References Cited, which, however, may not be currently applied as a basis for the following rejections. While these references were considered during the examination of this application and are deemed relevant to the claimed subject matter, they are not presently being applied as a basis for rejection in this Office action. The pertinence of these documents, however, may be revisited, and they may be applied in subsequent Office actions, particularly in light of any amendments or further clarification of the claimed invention.
Response to Arguments
Applicant's arguments filed 8/17/2026 have been fully considered but they are not persuasive.
1. Rejection Under 35 U.S.C. § 112(b)
Applicant argues under MPEP § 2173.04 (citing In re Miller) that the terms "X-shaped" and "Y-shaped" pattern structures are broad rather than indefinite. While the Office agrees that claim breadth alone does not constitute indefiniteness, a claim limitation must still define the subject matter with reasonable certainty so that a person of ordinary skill in the art (POSITA) can determine its physical scope.
Absence of Structural Boundaries: Illustrating the claimed "X-shaped" and "Y-shaped" pattern structures solely as featureless rectangular blocks in a 2D cross-section (e.g., element 1151 in FIG. 2) fails to provide any structural or geometric boundaries. The claims and drawings omit physical dimensions, aspect ratios, branch angles, or top-down planar contours necessary to define what constitutes an "X" or "Y" configuration. Consequently, a POSITA cannot ascertain which physical geometries fall within or outside the scope of the claims.
Functional Claiming via Generic Placeholder (MPEP § 2181 / MPEP § 2173.05(g)): Under MPEP § 2173.05(g), defining a physical structure primarily by its functional output (regulating light emergence angle or wavelength) without reciting the structural features required to achieve that output creates ambiguity. Because FIG. 2 depicts these structures merely as featureless solid blocks, the terms act as generic placeholders lacking sufficient structural definition to perform the recited optical function, rendering the claim scope indefinite under 35 U.S.C. § 112(b).
2. Rejection Under 35 U.S.C. § 112(a) and Drawing Objection Under 37 C.F.R. § 1.83(a)
Applicant contends that under 37 C.F.R. § 1.83(a), the claimed shapes are "conventional features" that may be represented by labeled rectangular boxes. This argument is unpersuasive:
Non-Conventional Point of Novelty: The "conventional feature" provision of 37 C.F.R. § 1.83(a) is intended for standard, well-known components where detailed illustration is non-essential to understanding the invention (e.g., generic power supplies or standard circuit blocks). Here, the specific planar geometries of the metasurface structures are point-of-novelty limitations designed to dictate light behavior. Because the physical geometry directly controls the optical performance, the shapes are essential structural features that must be shown pursuant to 37 C.F.R. § 1.83(a).
Failure to Satisfy the Labeled Box Exception: Even assuming arguendo that 37 C.F.R. § 1.83(a) applied, FIG. 2 does not contain a labeled representation identifying the structures as "X-shaped" or "Y-shaped". Lead line 1151 points only to generic cross-sectional blocks within layer 115. A featureless cross-section without explicit graphic labeling on the drawing sheet does not constitute a "labeled representation".
Lack of Written Description (35 U.S.C. § 112(a)): A 2D cross-sectional view showing uniform rectangular blocks does not convey to a POSITA that the inventor was in possession of the specifically claimed alternating X-shaped and Y-shaped metasurface patterns as of the filing date.
Accordingly, claims 1–20 are rejected under 35 U.S.C. § 112(b) for indefiniteness and 35 U.S.C. § 112(a) for lack of written description, and the drawings remain objected to under 37 C.F.R. § 1.83(a).
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1–4, 6–20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the enablement requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to enable one skilled in the art to which it pertains, or with which it is most nearly connected, to make and/or use the invention.
Independent claim 1 recites specific metasurface pattern geometries, including an "X-shaped pattern structure" and a "Y-shaped pattern structure". However, the application drawings fail to disclose these specific planar shapes. FIG. 2 only illustrates generic, featureless cross-sectional blocks designated by reference numeral 1151.
Disclosing featureless, two-dimensional rectangular blocks in cross-section does not convey to a person of ordinary skill in the art (POSITA) that the inventor was in possession of the specific alternating X-shaped and Y-shaped planar structures as of the filing date. Because the specification lacks any detailed top-down view or structural illustration showing these specific shape geometries, the written description requirement is not satisfied.
Claims 1–4, 6–20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Illustrating the claimed "X-shaped" and "Y-shaped" structures solely as featureless rectangular blocks in a 2D cross-section (e.g., element 1151 in FIG. 2) fails to provide physical or geometric boundaries, such as stroke widths, branch angles, aspect ratios, or planar contours. Without structural boundaries in the specification or drawings, a POSITA cannot ascertain which physical geometries fall within or outside the scope of the claims.
The structure designated by reference numeral 1151 in FIG. 2 is literally a featureless "black box" drawn as a generic rectangle. Under MPEP § 2181, defining a claim limitation using a purely generic structural placeholder—a "black box" that could literally be anything—to perform a recited function without disclosing the specific structural details required to execute that function renders the claim indefinite under 35 U.S.C. 112(b). Depicting these metasurface pattern elements as featureless solid blocks reduces the recited shapes to functional black boxes lacking the physical structure necessary to regulate light emergence angle or wavelength.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the “variant” “X”, “Y”, “F”, etc.. shaped patterns and structures [throughout numerous claims] and must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 2, 6, 10, 12-16, 18-20 is/are is/are rejected under 35 U.S.C. 103 as being unpatentable over Bonar et al (US 20150008392 A1).
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CLAIM 1. Bonar teaches a Micro-LED chip (Figs 2-10; e.g. Fig. 3b), comprising an LED chip structure (¶9), wherein:
the Micro-LED chip further comprises a first metasurface conductive structure layer 354 (Bonar discloses an "integrated transparent electrically conductive layer" ¶14 that can be patterned to form "2D photonic crystal structures" ¶42-46.), and the first metasurface conductive structure layer comprises:
a first conductive layer 354, wherein the first conductive layer is electrically bonded to a light emergence face of the LED chip structure (¶22&34 - "transparent conductive oxide (TCO) layer" [e.g. transparent caps 354] that forms part of the ohmic contact to the device anode and is “on top of a conductive layer providing an ohmic contact to the device anode".); and
a metasurface structure, wherein the metasurface structure comprises a first metasurface structure, wherein the first conductive layer comprises a plurality of first pattern structures, wherein the plurality of first pattern structures are distributed in a direction parallel to the light emergence face and form the first metasurface structure, wherein each first pattern structure comprises an X-shaped pattern structure and a Y- shaped pattern structure, wherein in a specified direction parallel to the light emergence face, the Y-shaped pattern is formed, wherein dimensions of the X-shaped pattern structure and the Y-shaped pattern structure are both 1 nm-1 um, and wherein the X-shaped pattern structure and the Y-shaped pattern structure are alternately arranged along the specified direction, (Under BRI (MPEP §2111), because th application fils to structurally define or illustrate the claimed pattern geometry beyond a genic bloc (applicant’s Fig. 2, element 1151), Bonar’s patterned conductive/dielectric layer 354 (¶42-46) reads on and satisfies this limitation.)
wherein the metasurface structure is configured to be stacked and/or integrated with the first conductive layer, and is at least used for regulating an emergence angle and/or wavelength of light ejected from the light emergence face (¶68 “Generally speaking, the present invention resides in the provision of using a transparent (e.g. visible light transparent) conductive cap structure on top of a light emitting diode to improve light extraction and the amount of light emitted.”).
To the extend that Bonar does not explicitly disclose the specific geometric shapes (Such as X-shaped or Y-shaped shapes and/or patterns) recited in the claims, Bonare discloses patterned conductive and dielectric metasurface layers/2D photonic crystal structures for regulating light extraction and emission (¶42-46, 68; element 354).
It would have been obvious to a POSITA at the time of the invention to select specific geometric shapes, including standard X-shaped, Y-shaped, of polygonal configurations, for patterned elements of Bonar’s metasurface/photonic structure. One of ordinary skill in the art would routinely optimize the physical geometry of surface features to achieve desired optical interference, scattering, or light extraction characteristics, as adjusting feature shapes represents a routine design choice with predictable optical results (MPEP §2144.04).
CLAIM 2. Bonar teaches a Micro-LED chip according to claim 1, wherein the first conductive layer comprises a metal or non-metal conductive layer (Fig. 3b- ITO transparent caps 354).
CLAIM 6. Bonar teaches a Micro-LED chip according to claim 1, wherein: the first metasurface conductive structure layer further comprises a transparent dielectric layer stacked on the first conductive layer (¶52-53 – “The light emitter structure may then be covered with a thin insulating layer such as silicon dioxide or silicon nitride... on top of the TCO lens “).
CLAIM 10. Bonar teaches a Micro-LED chip according to claim 1, further comprising a second metasurface conductive structure layer (Fig. 9 – demonstrates a plurality of metasurface conductive structures), wherein the LED chip structure has a first face and a second face opposite to the first face, the first face is the light emergence face, and the second face is electrically bound with a LED driving mechanism through a second conductive layer . (Fig 9 – LEDs require a “driving mechanism” to operate.)
CLAIM 12. Bonar teaches a Micro-LED chip according to claim 1, wherein: the LED chip structure comprises a first doped semiconductor layer, an active layer and a second doped semiconductor layer, the first doped semiconductor layer, the active layer and the second doped semiconductor layer are stacked sequentially along a set direction, a side surface of the first doped semiconductor layer or the second doped semiconductor layer far away from the active layer is the light emergence face; and/or the first conductive layer forms an ohmic contact with the light emergence face of the LED chip structure; and/or the LED chip structure comprises a GaN-based LED chip structure (Figs. 2-20 - Bonar describes a Gallium Nitride (GaN) based LED with p-doped and n-doped layers and an "active layer".).
CLAIM 13. Bonar teaches a method for preparing the Micro-LED chip according to claim 1, comprising: making a LED chip structure; and disposing a first conductive layer and a metasurface structure on the light emergence face of the LED chip structure, wherein the metasurface structure is configured to be stacked and/or integrated with the first conductive layer (The recited method steps are inherent to a completed stacked micro LED structure as shown in Bonar fig. 3b. Bonar describes a method of manufacturing a light emitting structure including providing an integrated transparent electrically conductive layer and patterning it (e.g. claims 44, 45 and 47)).
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CLAIM 14. Bonar teaches a method according to claim 13, wherein the metasurface structure comprises a second metasurface structure, and the method specifically comprises:
when the first conductive layer is made on the light emergence face of the LED chip structure, forming a plurality of first pattern structures in the first conductive layer, and distributing the plurality of first pattern structures along a direction parallel to the light emergence face, thereby forming the first metasurface structure The recited method steps are inherent to a completed stacked micro LED structure as shown in Bonar fig. 3b. Bonar describes a method of manufacturing a light emitting structure including providing an integrated transparent electrically conductive layer and patterning it (e.g. claims 44, 45 and 47)).;
alternatively, the metasurface structure comprises a second metasurface structure, and the method specifically comprises:
disposing a transparent dielectric layer on the first conductive layer, forming a plurality of second pattern structures in the transparent dielectric layer, and distributing the plurality of second pattern structures in the direction parallel to the light emergence face, thereby forming the second metasurface structure The recited method steps are inherent to a completed stacked micro LED structure as shown in Bonar fig. 3b. Bonar describes a method of manufacturing a light emitting structure including providing an integrated transparent electrically conductive layer and patterning it (e.g. claims 44, 45 and 47));
disposing a transparent dielectric layer on the first conductive layer, forming the plurality of second pattern structures in the transparent dielectric layer, and distributing the plurality of second pattern structures in the direction parallel to the light emergence face, thereby forming the second metasurface structure The recited method steps are inherent to a completed stacked micro LED structure as shown in Bonar fig. 3b. Bonar describes a method of manufacturing a light emitting structure including providing an integrated transparent electrically conductive layer and patterning it (e.g. claims 44, 45 and 47)).
CLAIM 15. Bonar teaches a method according to claim 13, further comprising: electrically binding a side surface of the LED chip structure opposite to the light emergence face with a LED driving mechanism through a second metasurface conductive structure layer (Fig. 9 – depicts a mounted micro-LEDs); wherein the second metasurface conductive structure layer comprises a second conductive layer and a third metasurface structure formed on a side surface of the second conductive layer close to the LED chip structure or on a side surface of the LED chip structure opposite to the light emergence face (Figs. 2-10).
CLAIM 16. Bonar teaches a Micro-LED device, comprising the Micro-LED chip according to claim 1 (Figs. 2-10).
CLAIM 18. Bonar teaches a Micro-LED chip according to claim 2, wherein: the first metasurface conductive structure layer further comprises a transparent dielectric layer stacked on the first conductive layer (Figs. 2-10).
CLAIM 19. Bonar teaches a Micro-LED chip according to claim 3, wherein: the first metasurface conductive structure layer further comprises a transparent dielectric layer stacked on the first conductive layer (Figs. 2-10 & ¶52-53 – “The light emitter structure may then be covered with a thin insulating layer such as silicon dioxide or silicon nitride... on top of the TCO lens “).
CLAIM 20. Bonar teaches a Micro-LED chip according to claim 18, wherein: the metasurface structure comprises a second metasurface structure, the transparent dielectric layer comprises a plurality of second pattern structures, and the plurality of second pattern structures are distributed in a direction parallel to the light emergence face and form the second metasurface structure (Figs. 2-10 & ¶52-53 – “The light emitter structure may then be covered with a thin insulating layer such as silicon dioxide or silicon nitride... on top of the TCO lens “).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 3-4, 7-9, 11, 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Bonar et al (US 20150008392 A1) in view of Iguchi et al (US 20190267357 A1).
CLAIM 3. Bonar teaches a Micro-LED chip according to claim 1, wherein: the first conductive layer comprises a metal or non-metal conductive layer (e.g. ITO - Bonar Figs. 2-10).
Bonar is silent regarding a metal conductive layer with a thickness below 20 nm that extends continuously parallel to the light emergence face. However, paragraph [0073] of Bonar teaches that thickness is a known, optimizable parameter. Furthermore, Iguchi (paragraph [0078]) explicitly teaches that forming ITO electrode layers below 20 nm was routine, specifically disclosing a layer of "approximately 5 nm."Therefore, it would have been obvious to a person of ordinary skill in the art to determine the optimal thickness through routine experimentation. Because thickness is a result-effective variable, and there is no evidence that a <20 nm thickness is critical or produces unexpected results, adjusting this parameter is a matter of routine optimization, not invention. See MPEP § 2144.05; In re Applied Materials, Inc., 692 F.3d 1289, 1295 (Fed. Cir. 2012).
Given the teaching of the references, it would have been obvious to determine the optimum thickness, temperature as well as condition of delivery of the layers involved. See In re Aller, Lacey and Hall (10 USPQ 233-237) “It is not inventive to discover optimum or workable ranges by routine experimentation.” Note that the specification contains no disclosure of either the critical nature of the claimed ranges or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the Applicant must show that the chosen dimensions are critical. In re Woodruff, 919 f.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Any differences in the claimed invention and the prior art may be expected to result in some differences in properties. The issue is whether the properties differ to such an extent that the difference is really unexpected. In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986).
Applicants have the burden of explaining the data in any declaration they proffer as evidence of non-obviousness. Ex parte Ishizaka, 24 USPQ2d 1621, 1624 (Bd. Pat. App. & Inter. 1992).
An Affidavit or declaration under 37 CFR 1.132 must compare the claimed subject matter with the closest prior art to be effective to rebut a prima facie case of obviousness. In re Burckel, 592 F.2d 1175, 201 USPQ 67 (CCPA 1979).
4. Bonar in view of Iguchi teaches a Micro-LED chip according to claim 2, wherein: a material of the metal conductive layer comprises a combination of any one or more of indium, tin, silver, platinum, gold, titanium, aluminum, nickel, chromium, molybdenum and copper (Bonar – ITO; Iguchi – gold, ITO, aluminum, etc); and/or a thickness of the metal conductive layer is 0.1 nm-20 nm,; and a material of the non-metal conductive layer comprises ITO; and/or, a thickness of the non-metal conductive layer is 1 nm-500 nm (Iguchi – Thickness within the range were known options.).
Given the teaching of the references, it would have been obvious to determine the optimum thickness, temperature as well as condition of delivery of the layers involved. See In re Aller, Lacey and Hall (10 USPQ 233-237) “It is not inventive to discover optimum or workable ranges by routine experimentation.” Note that the specification contains no disclosure of either the critical nature of the claimed ranges or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the Applicant must show that the chosen dimensions are critical. In re Woodruff, 919 f.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
CLAIM 7. Bonar in view of Iguchi teaches a Micro-LED chip according to claim 6, wherein: the metasurface structure comprises a second metasurface structure, the transparent dielectric layer comprises a plurality of second pattern structures, and the plurality of second pattern structures are distributed in a direction parallel to the light emergence face and form the second metasurface structure.
CLAIM 8. Bonar in view of Iguchi teaches a Micro-LED chip according to claim 7, wherein the first metasurface structure is formed in the first conductive layer and at least used for regulating one of the emergence angle and wavelength of the light ejected from the light emergence face; and the second metasurface structure, wherein the second metasurface structure is at least used for regulating the other one of the emergence angle and wavelength of the light ejected from the light emergence face; and/or each second pattern structure comprises a circular pattern structure with a F-shaped through hole embedded in a center of the circular pattern structure, and in a specified direction parallel to the light emergence face, the variant F-shaped through hole is in a shape formed by rotating a F shape by 30° clockwise, a dimension of the F-shaped through hole is 1-200 nm, a plurality of circular pattern structures are arranged periodically, and periods in the specified direction and a direction perpendicular to the specified direction are both 1 nm-1 μm; (Bonar explicitly teaches that structured layers patterned to form refractive, diffractive, or 2D photonic crystal structures are utilized to enhance light extraction. While the claim (previously rejected under 112(b)) recites specific, arbitrary shapes such as 'F' or 'K,' the selection of such geometry within the disclosed photonic crystal framework constitutes a routine optimization of the optical response (e.g., adjusting meta-atom shapes via adjoint or topology optimization to achieve desired light extraction). To a person of ordinary skill in the art (POSITA), modifying the specific cross-section of patterned elements is merely a matter of engineering design choice to tune refractive or diffractive properties.).
CLAIM 9. Bonar in view of Iguchi teaches a Micro-LED chip according to claim 6, wherein: a material of the transparent dielectric layer comprises a combination of any one or more of silicon oxide, silicon nitride, aluminum nitride, aluminum oxide, gallium oxide, titanium oxide, and hafnium oxide (Figs. 2-10 & ¶52-53 – “The light emitter structure may then be covered with a thin insulating layer such as silicon dioxide or silicon nitride... on top of the TCO lens “); and/or the transparent dielectric layer has a thickness of 0.1 nm-1 μm (Given the teaching of the references, it would have been obvious to determine the optimum thickness, temperature as well as condition of delivery of the layers involved. See In re Aller, Lacey and Hall (10 USPQ 233-237) “It is not inventive to discover optimum or workable ranges by routine experimentation.” Note that the specification contains no disclosure of either the critical nature of the claimed ranges or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the Applicant must show that the chosen dimensions are critical. In re Woodruff, 919 f.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).).
CLAIM 11. Bonar in view of Iguchi teaches a Micro-LED chip according to claim 10, wherein: the second face of the LED chip structure is electrically bound with the LED driving mechanism through the second metasurface conductive structure layer, the second metasurface conductive structure layer comprises the second conductive layer and a third metasurface structure, the third metasurface structure is disposed on a side surface of the second conductive layer close to the LED chip structure or the second face of the LED chip structure, and is at least used for reflecting light emitted by the LED chip structure toward the second metasurface conductive structure layer; and the third metasurface structure comprises a plurality of third pattern structures distributed in a direction parallel to the second face, and a dimension of the third pattern structure is 1 nm-1 μm; and the third pattern structure comprises an equilateral triangle pattern structure and a equilateral triangle pattern structure, the equilateral triangle pattern structure and the equilateral triangle pattern structure are alternately arranged along a specified direction parallel to the second face, wherein a X-shaped through hole is embedded in a center of the equilateral triangle pattern structure, the X-shaped through hole is in a shape obtained by rotating a X shape by 45° clockwise, a Z-shaped through hole is embedded in a center of the equilateral triangle pattern structure, the equilateral triangle pattern structure is a shape obtained by rotating an equilateral triangle around a designated point by 90° clockwise, the Z-shaped through hole is in a shape obtained by rotating a Z-shape by 45° clockwise, a line length of the X-shaped through hole and the Z-shaped through hole is 1 nm-500 nm (Regarding the claimed [patterned reflective layer/TCO], Bonar explicitly discloses a reflective layer associated with a patterned TCO layer 8 and/or GaN layer 6. The claim’s inventive feature represents merely one of a finite number of known, predictable alternatives for enhancing light output/contact resistance in a LED, and therefore was obvious to try with a reasonable expectation of success based on the teachings of Bonar).
CLAIM 17. Bonar in view of Iguchi teaches a Micro-LED chip according to claim 3, wherein: a material of the metal conductive layer comprises a combination of any one or more of indium, tin, silver, platinum, gold, titanium, aluminum, nickel, chromium, molybdenum and copper (Bonar – ITO; Iguchi – gold, ITO, aluminum, etc) a thickness of the non-metal conductive layer is 1 nm-500 nm (Iguchi – Thicknesss within the range were known options.).
Given the teaching of the references, it would have been obvious to determine the optimum thickness, temperature as well as condition of delivery of the layers involved. See In re Aller, Lacey and Hall (10 USPQ 233-237) “It is not inventive to discover optimum or workable ranges by routine experimentation.” Note that the specification contains no disclosure of either the critical nature of the claimed ranges or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the Applicant must show that the chosen dimensions are critical.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JARRETT J STARK whose telephone number is (571)272-6005. The examiner can normally be reached 8-4 M-F.
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JARRETT J. STARK
Primary Examiner
Art Unit 2822
9/18/2026
/JARRETT J STARK/Primary Examiner, Art Unit 2898
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