DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 12 March, 2026 has been entered.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 12 March, 2026 was filed in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Response to Amendment
The Amendment filed 12 March, 2026 has been entered. Claims 1-2, 4-6, 8-18, and 20 remain pending in the application. Applicant’s amendments to the Claims have overcome each and every rejection under 35 USC § 102 previously set forth in the Final Office Action mailed 12 December, 2025. Examiner further acknowledges amendments to the claims which have been rejected upon further search and consideration.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-2, 4-5, 8-12, 16, 18, and 20 rejected under 35 U.S.C. 103 as being unpatentable over Rajan et al (U.S. Patent Pub. No. 2014/0192583), hereinafter referred to as Rajan, in view of Chuang et al (U.S. Patent No. 9,494,647), hereinafter referred to as Chuang.
In regard to claim 1, Rajan teaches a stacked DRAM device comprising: a set of dies arranged in a stack and comprising respective core DRAMs; and an interface die in the stack (Figs. 1, 2; Paragraph 0311; chips e.g. die; ¶ 0391 DRAM stack), the interface die including: command/address logic to receive external DRAM command/address signals from a DRAM memory controller (¶ 0343 lines 1-3; controller capable of DRAM control (i.e. DRAM controller) issues commands to buffer chip (i.e. interface die)) and generate internal DRAM command/address signals on internal command/address lines to the respective core DRAMs (¶ 0343 lines 2-4, interface die delays and then issues (generates) DRAM signals for chips), wherein the internal command/address lines include through silicon vias between the set of memory dies (¶ 1298, lines 1-5 stack is connected using through-silicon vias, meaning connected command/address lines would be as well, like in the configuration in Fig. 87 for separating an interface die from a DRAM die); encoding/decoding logic to decode write data received from a data bus and to encode read data for outputting to the data bus (Paragraph 0302 interface circuit emulates signals; Paragraph 0303 emulated signals include data signals and read/write operation signals; emulation would require some form of encode/decode to transform signal; Paragraph 0785, lines 9-14 buffer (interface) can include decoders; Paragraph 0326 example of address decoding); and read/write driver logic to receive the decoded write data from the encoding/decoding logic and to distribute the decoded write data to the respective core DRAMs, and to receive the read data from the respective core DRAMs for providing to the encoding/decoding logic (Paragraph 0616). Rajan ¶ 0597 discusses power management schemes, but lines 14-16 disclose that interface circuits may include output driver logic which a person of ordinary skill in the art would correlate to read/write operation. Additionally, Rajan discloses connecting stacked dies using through silicon vias (Paragraph 1298, lines 1-5), achieving the claimed limitation. Rajan ¶ 0946 discloses ECC using bits added to data words, and ¶ 1067 discloses storing data in a RAID configuration wherein data is stored across chips and a separate chip stores error correction codes, which would functionally result in storing a different subset of bits of the data word on a different chip (die), meaning read data must also functionally be received from different chips to verify ECC, achieving the claimed limitation.
Rajan does not disclose using a data bus inversion scheme, however Chuang teaches a memory array interface which includes data bus inversion circuitry which may encode read data from and decode write data to the memory array (Column 4, lines 1-15), achieving the claimed limitation. It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to combine the disclosure of Chuang in order to benefit from "reliable, high speed bit detection for performing data bit inversion" (Column 2, lines 57-58).
As for claim 2, the previously cited references teach the memory device of claim 1. Additionally, Rajan teaches an embodiment wherein the interface die includes an integrated core DRAM, wherein the read/write driver logic further communicates a portion of the decoded write data to the integrated core DRAM, and wherein the read/write driver logic further receives a portion of the read data from the integrated core DRAM. Paragraph 0321 discloses storing at least a portion of information from an operation in the interface circuit, which would require an integrated memory. Paragraph 0321, lines 1-4 disclose that the information is used in performing another operation, which would require communicating some portion of data to integrated memory and receiving some portion of data from it, achieving the claimed limitation. Additionally, the integrated memory would act as DRAM, as the memory may be used for repeating operations, and the buffer chip presents itself as an emulated single DRAM device (¶ 0311 lines 1-4).
As for claim 4, Rajan teaches the memory device of claim 1. Additionally, Rajan Fig. 3 shows memories arranged in two different ranks each having their own control channels, achieving the claimed limitation.
As for claim 5, the previously cited references teach the memory device of claim 1. Additionally, Rajan teaches an embodiment wherein at least one of the respective core DRAMs is configured to store a payload portion of the decoded write data and wherein at least one of the respective core DRAMs comprises a dedicated error correction code DRAM configured to store error correction code data of the decoded write data. Paragraph 1067 discloses storing data in a RAID configuration wherein data is stored across chips and a separate chip stores error correction code, achieving the claimed limitation.
As for claim 8, Rajan teaches a memory module comprising: a data bus interface for coupling to a memory controller via a data bus; and a set of stacked memory devices coupled to the data bus interface (Fig. 121A; Paragraph 0184; Paragraph 1254). For limitations directed to the stacked memory devices, applicant is directed to the rejection of claim 1 as the limitations are the same and are therefore rejected on the same rationale.
As for claim 9, the previously cited references teach the memory module of claim 8. Additionally, Rajan discloses an embodiment wherein the set of stacked DRAM devices are organized into a plurality of channels, each of the plurality of channels comprising at least two rows of stacked DRAM devices, and each of the at least two rows comprising two stacked DRAM devices operating in different ranks. (Fig. 210; Paragraph 1729 multiple ranks described), achieving the claimed limitation.
As for claim 10, Rajan teaches the memory module of claim 8. Additionally, Rajan Fig. 3 shows stacked memories arranged using two ranks, achieving the claimed limitation.
As for claim 11, Rajan teaches the memory module of claim 8. Additionally, Rajan Fig. 2 shows stacked memories arranged using four ranks, achieving the claimed limitation.
As for claim 12, applicant is directed to the rejection of claim 9, as the rejection addresses the limitations presented in claim 12. The rejection of claim 9 includes four channels with four stacked memory devices each.
As for claim 16, the previously cited references teach the memory module of claim 8. Additionally, Rajan teaches using spare memory modules (die stacks) in the event of a failure in a memory module that shows too many errors (Paragraph 0902). If implemented in the channel configuration of, for example, Fig. 210, spare modules would replace failed modules in each channel, achieving the claimed limitation.
As for claim 18, Rajan discloses a method for operating a stacked memory device, the method comprising: receiving, at an interface die of the stacked memory device from a data bus, a write command and encoded write data for writing to the memory device; processing the write command by command/address logic to generate an internal DRAM command/address signal on one or more internal command/address lines to respective core DRAMs in a set of memory dies of the stacked DRAM device (¶ 0343 lines 1-3; controller capable of DRAM control (i.e. DRAM controller) issues commands to buffer chip (i.e. interface die); ¶ 0343 lines 2-4, interface die delays and then issues (generates) DRAM signals for chips), wherein the internal command/address lines include through silicon vias between the set of memory dies (¶ 1298, lines 1-5 stack is connected using through-silicon vias, meaning connected command/address lines would be as well, like in the configuration in Fig. 87 for separating an interface die from a DRAM die); decoding, by encoding/decoding logic of the interface die, the encoded write data to generate decoded write data (Paragraph 0302 interface circuit emulates signals; Paragraph 0303 emulated signals include data signals and read/write operation signals; emulation would require some form of encode/decode to transform signal; Paragraph 0785, lines 9-14 buffer (interface) can include decoders; Paragraph 0326 example of address decoding); writing, by read/write logic of the interface die, different subsets of bits of the decoded write data to different core DRAMs in different dies of the stacked memory arranged in a stack (Paragraph 1067 discloses storing data in a RAID configuration wherein data is stored across chips); receiving, at the interface die of the stacked memory device, a read command for reading from the stacked memory device; processing the read command by the command/address logic to generate an internal DRAM command/address signal on the one or more internal command/address lines to the respective core DRAMs in the set of memory dies of the stacked DRAM device (¶ 0343 lines 1-3; controller capable of DRAM control (i.e. DRAM controller) issues commands to buffer chip (i.e. interface die); ¶ 0343 lines 2-4, interface die delays and then issues (generates) DRAM signals for chips); obtaining different subsets of bits of read data from the different core DRAMs in the different dies of the stacked memory device responsive to the read command; aggregating, by the read/write logic of the interface die, the different subset of bits of the read data to generate aggregated read data (RAID configuration would functionally require re-aggregating data for read requests); encoding, by the encoding/decoding logic of the interface die (reads would functionally require re-encoding of for example address data), the aggregated read data into encoded read data; and outputting, by the encoding/decoding logic, the encoded read data to the data bus (Fig. 119C data bus). Additionally, Rajan discloses connecting stacked dies using through silicon vias (Paragraph 1298, lines 1-5), achieving the claimed limitation. Rajan ¶ 0946 also discloses ECC using bits added to data words i.e. transferring data words, achieving the claimed limitation.
Rajan does not disclose using a data bus inversion scheme, however Chuang teaches a memory array interface which includes data bus inversion circuitry which may encode read data from and decode write data to the memory array (Column 4, lines 1-15), achieving the claimed limitation. It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to combine the disclosure of Chuang in order to benefit from "reliable, high speed bit detection for performing data bit inversion" (Column 2, lines 57-58).
As for claim 20, the previously cited references teach the method of claim 18. Additionally, Rajan Paragraph 1067 discloses storing data in a RAID configuration wherein data is stored across chips and a separate chip stores error correction codes, which would functionally result in selecting the error correction code chip to write ECC data to. Rajan ¶ 0946 also discloses ECC using bits added to data words i.e. transferring data words, achieving the claimed limitation. As for claim 20, the previously cited references teach the method of claim 18. Additionally, Rajan Paragraph 1067 discloses storing data in a RAID configuration wherein data is stored across chips and a separate chip stores error correction codes, which would functionally result in selecting the error correction code chip to write ECC data to.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Rajan in view of Chuang and Gupta et al (U.S. Patent Pub. No. 2008/0082707), hereinafter referred to as Gupta. The previously cited references teach the memory device of claim 1. They do not teach the remaining limitations of claim 6. However, Gupta teaches a memory system including multiple memory devices 103 (Fig. 1) which may utilize a data width that is not a power of 2 (Paragraph 0046), achieving the claimed limitation. It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to combine the teaching of Gupta in order to support a wider range of data widths and benefit from a high performance, scalable bus protocol (Paragraph 0031).
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Rajan in view of Chuang and Meaney et al (U.S. Patent Pub. No. 2014/0281325), hereinafter referred to as Meaney. The previously cited references teach the memory module of claim 8. Additionally, Rajan teaches arranging stacked memory devices into four channels having four memory devices each (Fig. 210). Rajan does not teach five channels having four memory devices. However, Meaney teaches five channels for accessing a plurality of memory devices (Paragraph 0028). When combined with the teaching of four memory devices per channel of Rajan, the claimed limitation is achieved. It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to combine the disclosure of Meaney in order to support additional memory channels and benefit from out-of-order or out-of-synchronization detection and correction (Paragraph 0027).
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Rajan in view of Chuang and Kinsley et al (U.S. Patent Pub. No. 2020/0212010), hereinafter referred to as Kinsley. The previously cited references teach the memory module of claim 8. Additionally, Rajan teaches arranging stacked memory devices into four channels having four memory devices each (Fig. 210). Rajan does not teach four channels having five memory devices. However, Kinsley teaches arranging five stacked memory devices on a single channel (Fig. 3C; Paragraph 0033), achieving the claimed limitation. It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to combine the disclosure of Kinsley in order to support more memory devices per channel and to benefit from a lowered load on a shared clock signal (Paragraph 0033, lines 13-19).
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Rajan in view of Chuang and Feldman et al (U.S. Patent No. 9,075,733), hereinafter referred to as Feldman. The previously cited references teach the memory module of claim 8. They do not teach the remaining limitations of claim 15. However, Feldman teaches storing metadata relating to physical and logical memory addresses in a separate memory device managed by a controller (Column 1, lines 41-51). When combined with the ability of the system of Rajan's disclosure to access and control multiple memory devices, the claimed limitation is achieved. It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to combine the disclosure of Feldman to be able to manage metadata by maintaining it in another memory if it exceeds the size of a given memory (Column 4, lines 44-48).
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Rajan in view of Chuang and Williams et al (U.S. Patent No. 6,397,290), hereinafter referred to as Williams. The previously cited references teach the memory module of claim 8. They do not teach the remaining limitations of claim 17. However, Williams teaches a system including a memory controller directly coupled with multiple memory banks on a bus, wherein one bank optionally stores ECC bits (see Figs. 3 and 4; Column 4, lines 20-35), achieving the claimed limitation. It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to combine the disclosure of Williams in order to provide ECC capability on a spare device and benefit from switching between ECC and normal data storage on a bank, increasing capacity and speed when necessary (Column 2, lines 23-30).
Response to Arguments
Applicant's arguments (see page 11 of response filed 12 March, 2026) with respect to the amended claims have been fully considered but they are not persuasive. The rejections of the claims have been updated to address the added limitations. Rajan explicitly discloses utilizing DRAM devices as described in the updated rejections. Rajan Figs. 182A-B show stacked dies utilizing through-silicon vias for connection (see ¶ 1625-1627). Rajan also discloses that the interface/buffer chip may issue commands to DRAM chips as addressed in updated rejections, meaning it must have some form of read/write driver logic. Rajan ¶ 1067, lines 4-8 disclose breaking up memory blocks for striping, which would functionally break up the data at some bit level, and would break up data words with ECC given that ECC data may be stored separately in this configuration and the cited portions disclose applying ECC parity to individual data words. Rajan ¶ 1298 discloses structure for a stacked memory device that includes an interface and different memories in different dies on a stack (see Fig. 127 including interface, discussing the controller of the same embodiment). One would recognize that this may correlate to the buffer chips previously disclosed, which also act as interfaces. Rajan ¶ 0301 defines the use of the terms interface and buffer chip for clarity. “Chips” and “dies” as known in the art may refer to very similar structures, and given the breadth of Rajan’s disclosure, one would recognize that methods directed to “chips” (which may be stacked in wire-bonded packages containing a die in the disclosure, see Figs. 179-180) could also be directed to “dies” (discussed in later figures 182A-B using TSVs for stacking). The limitation of cancelled claims 3 and 19 was previously rejected, and the rationale has been used to reject the limitation in the amended claims.
Conclusion
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/ZAKARIA MOHAMMED BELKHAYAT/Examiner, Art Unit 2139
/REGINALD G BRAGDON/Supervisory Patent Examiner, Art Unit 2139