Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Prior Art of Record
The applicant's attention is directed to additional pertinent prior art cited in the accompanying PTO-892 Notice of References Cited, which, however, may not be currently applied as a basis for the following rejections. While these references were considered during the examination of this application and are deemed relevant to the claimed subject matter, they are not presently being applied as a basis for rejection in this Office action. The pertinence of these documents, however, may be revisited, and they may be applied in subsequent Office actions, particularly in light of any amendments or further clarification of the claimed invention.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 10-11 & 14-20 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 10 introduces the term "orthotropic projection" (e.g., "...wherein the orthotropic projection of the first sub-line..."). Throughout the remaining independent and dependent claims (such as Claims 1, 5, 13, and 17), the structural orientation is defined using the geometric term "orthographic projection."
The term "orthotropic" has a distinct meaning in physics and materials science, referring to physical properties that differ along mutually perpendicular axes. The introduction of "orthotropic" in the context of spatial layout and geometric placement creates ambiguity and leaves the true meaning and boundaries of the claimed projection unclear.
Claim 11 contains an internal technical contradiction that renders the scope of the claim unclear. The claim states that "the third transistor and the fourth transistor are oxide transistors." However, the claim immediately goes on to state that "the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor and the eighth transistor are polycrystalline silicon transistors."
Because the third and fourth transistors cannot simultaneously be composed of oxide materials and polycrystalline silicon materials, the claim is contradictory and fails to distinctly define the metes and bounds of the structural components.
Claims 14–20 fail to maintain proper antecedent basis and structural consistency with the independent claim from which they depend. Independent Claim 13 is directed to "A display panel, comprising an array substrate..."
However, dependent Claim 14 begins with the preamble, "The array substrate according to claim 13..." each subsequent claim in this group (Claims 15–20) similarly depends from a claim that traces back to this preamble mismatch. Because Claim 13 defines the overall device as a display panel, a dependent claim cannot redefine the claimed subject matter as merely the sub-component array substrate. This structural mismatch creates ambiguity as to whether the scope of the dependent claims encompasses the entire display panel or only the array substrate layer, rendering the claims indefinite.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-5, 8-9, 11-17, 20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Duan (CN 114725181 A)
Claim 1. Duan teaches an array substrate, comprising a substrate and a plurality of sub-pixels arranged in an array on the substrate ("a display panel... comprising: a substrate 1; ... a plurality of pixel units 2 arranged in an array on the substrate 1;"),
wherein each of the sub-pixels comprises a first transistor, and a first oxide transistor and a second oxide transistor connected to the first transistor ("In each pixel unit 2, the pixel circuit 21 comprises a plurality of thin film transistors... the thin film transistor may include a driving transistor T1 and a switching transistor... a second transistor T2... a third transistor T3");
a drain electrode of the first oxide transistor is connected to a gate electrode of the first transistor, and is connected to a source electrode of the second oxide transistor a drain electrode of the second oxide transistor is connected to a drain electrode of the first transistor ("a third transistor T3 connected between the gate electrode of the driving transistor T1 and the first electrode of the driving transistor T1; a second transistor T2 connected between the data line and the second pole of the driving transistor T1; the gate of the driving transistor T1 is connected with the third transistor T3 through the first connecting line 3;"); and
the array substrate further comprises: a first connection line connected between the drain electrode of the first oxide transistor and the gate electrode of the first transistor ("the gate of the driving transistor T1 is connected with the third transistor T3 through the first connecting line 3;");
a second connection line connected between the drain electrode of the first oxide transistor and the source electrode of the second oxide transistor; a first scan line connected to a gate electrode of the first oxide transistor ("the second connecting wire 6, the second connecting wire 6 is formed with the first electrode and the second electrode of the driving transistor T1;"); and
a second scan line connected to a gate electrode of the second oxide transistor ("the second connecting wire 6, the second connecting wire 6 is formed with the first electrode and the second electrode of the driving transistor T1;");
wherein an orthographic projection of the first scan line on the substrate is separated from an orthographic projection of the first connection line and the second connection line on the substrate, and an orthographic projection of the second scan line on the substrate is separated from the orthographic projection of the first connection line and the second connection line on the substrate ("the positive projection of the first branch line 4 on the substrate is not overlapped with the positive projection of the first connection line 3 on the substrate; The positive projection of the second branch line 5 on the substrate does not overlap with the positive projection of the first connection line 3 on the substrate... the positive projection of the first scanning line Scan 2 on the substrate is not overlapped with the positive projection of the first connecting line 3 on the substrate... the first scanning line Scan 2 on the substrate of the orthographic projection and the second connection line 6 on the substrate of the positive projection does not overlap.").
Claim 2. Duan teaches the array substrate according to claim 1, wherein the first scan line and the second scan line extend in a first direction and are spaced apart in a second direction, the first direction is different from the second direction, and the first connection line extends in the second direction ("the first scanning line Scan 2 extending along the X direction. The X direction can be the width direction of the display panel... the extension of the data line Vdata in the Y direction. The Y direction can be the length direction of the display panel... the thickness direction of the display panel in the first connecting line 3, can save the space of X direction or Y direction"); and
the first scan line is located on a side of the first connection line away from the first transistor or the first oxide transistor, and/or the second scan line is located on a side of the first connection line away from the first transistor or the first oxide transistor (“the first scanning line Scan 2 is set on one side of the third connecting line far away from the base plate; ... or, The first scanning line Scan 2 is set on one side of the first connecting line 3 far away from the base plate.”).
Claim 3. Duan teaches the array substrate according to claim 2, wherein in the second direction, the first transistor and the first oxide transistor are respectively located at both ends of the first connection line ("The gate of the driving transistor T1 is connected to the third transistor T3 through the first connecting line 3."), and the first scan line and the second scan line are located on the side of the first connection line away from the first transistor ("The first scanning line Scan 2 is set on one side of the first connecting line 3 far away from the base plate.").
Claim 4. Duan teaches the array substrate according to claim 3, wherein in the second direction, the second oxide transistor is located between the first transistor and the first oxide transistor, the second connection line is connected between the first oxide transistor and the second oxide transistor ("the third transistor T3 is connected between the gate of the driving transistor T1 and the first pole of the driving transistor T1. The second transistor T2 is connected between the data line and the second pole of the driving transistor T1... the second connecting wire 6, the second connecting wire 6 is formed with the first electrode and the second electrode of the driving transistor T1;".), and the first scan line is located on a side of the second scan line away from the second connection line ("the first scanning line Scan 2 is set on one side of the third connecting line far away from the base plate... the second connection line 6 comprises a first region N1, wherein the first scanning line Scan 2 orthographic projection on the second connection line 6 at least partially overlap with the second connection line 6").
Claim 5. Duan teaches the array substrate according to claim 2, wherein the array substrate further includes a third connection line and a fourth connection line, the third connection line and the fourth connection line extend in the second direction, the third connection line is connected between the first scan line and the gate electrode of the first oxide transistor, the fourth connection line is connected between the second scan line and the gate electrode of the second oxide transistor (a first branch line 4 and a second branch line 5 connected with the first scanning line Scan 2; the first branch line 4 is formed with a gate of the third transistor T3, the second branch line 5 is formed with a gate of the second transistor T2; the gate of the third transistor T3 is connected with the first scanning line Scan 2 through the first branch line 4; the gate of the second transistor T2 is connected with the first scanning line Scan 2 through the second branch line 5;"),
an orthographic projection of the third connection line on the substrate is separated from the orthographic projection of the first connection line and the second connection line on the substrate, and an orthographic projection of the fourth connection line on the substrate is separated from the orthographic projection of the first connection line and the second connection line on the substrate (“the positive projection of the first branch line 4 on the substrate is not overlapped with the positive projection of the first connection line 3 on the substrate; The positive projection of the second branch line 5 on the substrate does not overlap with the positive projection of the first connection line 3 on the substrate”).
Claim 8. Duan teaches the array substrate according to claim 7, wherein the first gate electrode and the third gate electrode are arranged in the same layer, the second gate electrode and the fourth gate electrode are arranged in the same layer, the first sub-line and the first gate electrode are arranged in the same layer, the second sub-line and the second gate electrode are arranged in the same layer, the third sub-line and the third gate electrode are arranged in the same layer, the fourth sub-line and the fourth gate electrode are arranged in the same layer (“the first scanning line Scan 2 is set on the third connecting line 7 far away from one side of the base plate... the first scanning line Scan 2 and data line Vdata set on the storage capacitor Cst of the second electrode away from one side of the substrate, The first scanning line Scan 2 and the data line Vdata are set in different layers.”).
Claim 9. Duan teaches the array substrate according to claim 8, wherein the first scan line, the first gate electrode, and the second gate electrode are arranged in different layers, the second scan line, the third gate electrode, and the fourth gate electrode are arranged in different layers, the first scan line is connected to the first sub-line through a first connection node and is connected to the second sub-line through a second connection node ("the first scanning line Scan 2 is set on the third connecting line 7 far away from one side of the base plate... the first scanning line Scan 2 and data line Vdata set on the storage capacitor Cst of the second electrode away from one side of the substrate, The first scanning line Scan 2 and the data line Vdata are set in different layers."),
the second scan line is connected to one of the third sub-line and the fourth sub-line through a third connection node, the third sub-line is connected to the fourth sub-line through a fourth connection node (A discloses interlayer electrical communication through multi-layer structures and vias: "the first connecting line 3 and the second connecting line 6 are specifically connected through the through hole.").
Claim 11. Duan teaches the array substrate of claim 1, wherein each subpixel further comprises a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a storage capacitor and a compensation capacitor, wherein the third transistor and the fourth transistor are oxide transistors, and the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor and the eighth transistor are polycrystalline silicon transistors, the fourth transistors are first oxide transistors, and the third transistors are second oxide transistors ("the pixel circuit 21 comprises a driving transistor T1, a fourth transistor T4, a seventh transistor T7, a second transistor T2, a third transistor T3, a fifth transistor T5, a sixth transistor T6, and a storage capacitor Cst. ... the pixel circuit 21 may also be other forms of pixel circuit, such as 7T1C pixel circuit and 8T2C pixel circuit");
wherein a drain of the fourth transistor is connected with a first electrode plate of the storage capacitor and a first electrode plate of the compensation capacitance, the first electrode plate of the storage capacitor is integrally arranged with the gate of the first transistor, a second electrode plate of the compensation capacitance is connected with a gate of the second transistor, a second electrode plate of the storage capacitor is connected with a source of the fifth transistor, a drain of the fifth transistor is connected with a source of the first transistor, a drain of the first transistor is connected with a drain of the third transistor and a source of the sixth transistor, and a drain of the sixth transistor is connected with a drain of the seventh transistor, a source of the first transistor, a drain of the second transistor and a drain of the fifth transistor are all connected with a drain of the eighth transistor ("the third transistor T3 is connected between the gate of the driving transistor T1 and the first pole of the driving transistor T1. The second transistor T2 is connected between the data line and the second pole of the driving transistor T1. The gate of the driving transistor T1 is connected to the third transistor T3 through the first connecting line 3. ... the gate electrode of the driving transistor T1 is connected with the first electrode of the fourth transistor T4 through the first connecting line 3 and the second connecting line 6").
Claim 12. Duan teaches the array substrate of claim 1, further comprising: a first semiconductor layer, arranged on the substrate and comprising an active layer of the first transistor; a first metal layer, arranged on one side of the first semiconductor layer far away from the substrate, and the first metal layer comprising a gate of the first transistor; a second metal layer, arranged on one side of the first metal layer far away from the first semiconductor layer; a second semiconductor layer, arranged on one side of the second metal layer far away from the first metal layer, and the second semiconductor layer comprising an active layer of the first oxide transistor, an active layer of the second oxide transistor, a first connecting wire and a second connecting line; a third metal layer, arranged on one side of the second semiconductor layer far away from the second metal layer, and a gate of the first oxide transistor and a gate of the second oxide transistor are formed in the third metal layer and the second metal layer; a fourth metal layer, arranged on one side of the third metal layer far away from the second semiconductor layer, and comprising the first scan line and the second scan line ("the display panel an active layer, a gate layer, a first metal layer, a second metal layer and a third metal layer, which sequentially arranged on one side of the substrate in a laminated manner. The active layer may be a silicon substrate layer such as a P-Si layer. The gate layer is used for forming the gate of the driving transistor T1 and the switching transistor... The first metal layer... the second metal layer... the third metal layer... the power supply line respectively set on the second metal layer and the third metal layer.").
Claim 13. Duan teaches the display panel, comprising an array substrate, the array substrate comprising a substrate and a plurality of sub-pixels arranged in an array on the substrate (a display panel, comprising: a substrate; ... a plurality of pixel units arranged in an array on the substrate;"),
wherein each of the sub-pixels comprises a first transistor, and a first oxide transistor and a second oxide transistor connected to the first transistor; a drain electrode of the first oxide transistor is connected to a gate electrode of the first transistor, and is connected to a source electrode of the second oxide transistor; a drain electrode of the second oxide transistor is connected to a drain electrode of the first transistor; the array substrate further comprises: a first connection line connected between the drain electrode of the first oxide transistor and the gate electrode of the first transistor; a second connection line connected between the drain electrode of the first oxide transistor and the source electrode of the second oxide transistor; a first scan line connected to a gate electrode of the first oxide transistor; and a second scan line connected to a gate electrode of the second oxide transistor; wherein an orthographic projection of the first scan line on the substrate is separated from an orthographic projection of the first connection line and the second connection line on the substrate, and an orthographic projection of the second scan line on the substrate is separated from the orthographic projection of the first connection line and the second connection line on the substrate (Similarly to claim 1, Duan teaches a third transistor T3, driving transistor T1, second transistor T2, first connecting line 3, second connecting line 6, scanning line Scan 2, first branch line 4, and second branch line 5 configured in the exact manner described..
Claim 14. Duan teaches the array substrate according to claim 13, wherein the first scan line and the second scan line extend in a first direction and are spaced apart in a second direction, the first direction is different from the second direction, and the first connection line extends in the second direction; and the first scan line is located on a side of the first connection line away from the first transistor or the first oxide transistor, and/or the second scan line is located on a side of the first connection line away from the first transistor or the first oxide transistor (Similarly to Claim 2: Duan describes the X-direction and Y-direction routing orientations and layer relationships relative to the first connecting line.).
Claim 15. Duan teaches the array substrate according to claim 14, wherein in the second direction, the first transistor and the first oxide transistor are respectively located at both ends of the first connection line, and the first scan line and the second scan line are located on the side of the first connection line away from the first transistor (Similarly to Claim 3: Duan describes the connection of the gate of T1 to T3 through line 3, with Scan 2 situated on the far side away from the base plate.).
Claim 16. Duan teaches the array substrate according to claim 15, wherein in the second direction, the second oxide transistor is located between the first transistor and the first oxide transistor, the second connection line is connected between the first oxide transistor and the second oxide transistor, and the first scan line is located on a side of the second scan line away from the second connection line (Similarly to Claim 4: Duan defines the relative arrangement of T1, T2, T3, and connecting lines 3 and 6 alongside the overlapping shield zone of Scan 2.).
Claim 17. Duan teaches the array substrate according to claim 14, wherein the array substrate further includes a third connection line and a fourth connection line, the third connection line and the fourth connection line extend in the second direction, the third connection line is connected between the first scan line and the gate electrode of the first oxide transistor, the fourth connection line is connected between the second scan line and the gate electrode of the second oxide transistor, an orthographic projection of the third connection line on the substrate is separated from the orthographic projection of the first connection line and the second connection line on the substrate, and an orthographic projection of the fourth connection line on the substrate is separated from the orthographic projection of the first connection line and the second connection line on the substrate (Similarly to Claim 5: Duran describes the non-overlapping projection properties of branch lines 4 and 5 relative to connection line 3.).
Claim 20. Duan teaches the array substrate according to claim 19, wherein the first gate electrode and the third gate electrode are arranged in the same layer, the second gate electrode and the fourth gate electrode are arranged in the same layer, the first sub-line and the first gate electrode are arranged in the same layer, the second sub-line and the second gate electrode are arranged in the same layer, the third sub-line and the third gate electrode are arranged in the same layer, the fourth sub-line and the fourth gate electrode are arranged in the same layer (Similarly to Claim 8: Duan fully sets forth that branch lines 4 and 5 and their respective gate nodes are formed in identical layers to achieve simpler manufacturing and save on overall display thickness.).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 6-7, 10, 18-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Duan (CN 114725181 A).
Claim 6. Duan teaches the array substrate according to claim 5, however may be unclear in teaching wherein the gate electrode of the first oxide transistor includes the first gate electrode and the second gate electrode arranged corresponding to each other, the first gate electrode is electrically connected to the second gate electrode, and the third connection line is electrically connected to one of the first gate electrode and the second gate electrode; and the gate electrode of the second oxide transistor includes the third gate electrode and the fourth gate electrode arranged corresponding to each other, the third gate electrode is electrically connected to the fourth gate electrode, and the fourth connection line is electrically connected to one of the third gate electrode and the fourth gate electrode.
Duan discloses that components can be constructed in a multiple-layer structure to provide flexibility and electrical coupling: "...the power supply line ELVDD comprises a first wiring layer and a second wiring layer, the first wiring layer and the first connecting wire 3 are set at the same layer; the second wiring layer is set on one side of the first connecting line 3 away from the base plate."
A POSITA)would find it obvious to apply this multi-layer structural teaching to the gate electrodes to construct them as a first and second gate electrode (or third and fourth) connected to one another. Specifically, forming gate electrodes or lines via multiple interconnected conductive paths or layer regions represents a routine design choice and architectural variation. A POSITA would readily implement this to modify capacitance, reduce line resistance, or ease wiring congestion, as doing so requires only the straightforward application of known multi-layer fabrication principles routinely used in array substrate manufacturing.
Claim 7. Duan teaches the array substrate according to claim 5, however may be unclear in the teaching wherein the gate electrode of the first oxide transistor includes a first gate electrode and a second gate electrode arranged corresponding to each other, the third connection line includes a first sub-line and a second sub-line, the first sub-line is connected between the first scan line and the first gate electrode, and the second sub-line is connected between the first scan line and the second gate electrode; and the gate electrode of the second oxide transistor includes a third gate electrode and a fourth gate electrode arranged corresponding to each other, the fourth connection line includes a third sub-line and a fourth sub-line, the third sub-line is connected between the second scan line and the third gate electrode, and the fourth sub-line is connected between the second scan line and the fourth gate electrode.
Duan teaches an array substrate comprising a first oxide transistor with a gate electrode and a second oxide transistor with a gate electrode.
Duan may not explicitly disclose dividing the connecting lines into specific "sub-lines" that connect a single scan line to split (divided) gate electrodes for each of the oxide transistors.
However, it would have been obvious to a person having ordinary skill in the art at the time of the invention to modify Duan's device to divide the connecting lines into corresponding sub-lines. Duan establishes the practice of distributing electrical connection paths across multiple sub-regions or layer distributions (e.g., "the power line located in the second area comprises a first wiring layer or a second wiring layer...").
Dividing a connecting branch line into multiple sub-lines to feed multi-part nodes or individual sub-gates relies on standard routing adjustments and known design choices MPEP § 2144.04. Adjusting the number of sub-lines to connect a single node (such as a scan line) to multiple physical gates simply configures the routing to accommodate physical layout demands, which requires only ordinary electrical routing skill and does not yield any unexpected results.
Claim 10. Duan teaches the array substrate of claim 7, however may be unclear in the teaching of wherein the orthotropic projection of the first sub-line on the substrate overlaps at least partially with the orthotropic projection of the second sub-line on the substrate, and the orthotropic projection of the third sub-line on the substrate overlaps at least partially with the orthotropic projection of the fourth sub-line on the substrate.
With respect to claim 7, Duan teaches the array substrate, including a first sub-line, a second sub-line, a third sub-line, and a fourth sub-line. However, Duan does not expressly teach that the orthotropic projection of the first sub-line overlaps at least partially with the second, or that the third overlaps at least partially with the fourth.
Duan discloses a substrate architecture that deliberately overlaps conductive lines to manage routing, optimize physical space, and provide structural shielding. Specifically, Duan teaches: "wherein the positive projection of the first scanning line on the second connecting line is at least partially overlapped with the second connecting line, and overlapped with the first area; The orthographic projection of the third connecting line on the substrate covers the orthographic projection of the first area of the second connecting line on the substrate."
A Person Having Ordinary Skill in the Art (PHOSITA) would immediately recognize that stacking or deliberately overlapping sub-lines so their projections intersect is a recognized, predictable engineering solution to compress the layout footprint, minimize parasitic capacitance, and maximize the substrate's usable physical space. Therefore, it would have been obvious to a PHOSITA to modify the sub-line arrangement of Duan to employ the partial or full overlapping projections taught by A in order to achieve these expected and well-documented optimization benefits.
Claim 18. “Duan teaches the array substrate array substrate according to claim 17, however may be silent upon wherein the gate electrode of the first oxide transistor includes the first gate electrode and the second gate electrode arranged corresponding to each other, the first gate electrode is electrically connected to the second gate electrode, and the third connection line is electrically connected to one of the first gate electrode and the second gate electrode; and the gate electrode of the second oxide transistor includes the third gate electrode and the fourth gate electrode arranged corresponding to each other, the third gate electrode is electrically connected to the fourth gate electrode, and the fourth connection line is electrically connected to one of the third gate electrode and the fourth gate electrode.”
Such a configuration would have been obvious to a PHOSITA in view of Duan. Duan discloses forming components in a multi-layer structure to provide flexibility and electrical coupling, specifically teaching that "the power supply line ELVDD comprises a first wiring layer and a second wiring layer, the first wiring layer and the first connecting wire 3 are set at the same layer; the second wiring layer is set on one side of the first connecting line 3 away from the base plate."
Routine Modification: Modifying a component to include multiple interconnected conductive paths, segment pieces, or layer regions is a routine architectural variation. A skilled artisan would employ this to adjust capacitance, reduce line resistance, or ease wiring congestion.
The use of multi-layer or multi-segment electrode pieces to create unified nodes represents a known, result-effective design choice. Modifying the structural routing of Duan to utilize this multi-layer configuration falls within the ordinary creativity and design variations expected of a PHOSITA.
Therefore, it would have been obvious to a skilled artisan to apply the multi-layer routing principles taught by Duan to the claimed structure to achieve predictable functional and electrical benefits.
Claim 19. Duan teaches the array substrate array substrate according to claim 17, however may be unclear on wherein the gate electrode of the first oxide transistor includes a first gate electrode and a second gate electrode arranged corresponding to each other, the third connection line includes a first sub-line and a second sub-line, the first sub-line is connected between the first scan line and the first gate electrode, and the second sub-line is connected between the first scan line and the second gate electrode; and the gate electrode of the second oxide transistor includes a third gate electrode and a fourth gate electrode arranged corresponding to each other, the fourth connection line includes a third sub-line and a fourth sub-line, the third sub-line is connected between the second scan line and the third gate electrode, and the fourth sub-line is connected between the second scan line and the fourth gate electrode.
These specific geometric and routing configurations would have been obvious to a person of ordinary skill in the art based on Duan applied to Claim 7. In Claim 7, Duan teaches trace separation configurations (e.g., branch lines not overlapping with connection lines on the substrate). Duan establishes the practice of distributing electrical connection paths across multiple sub-regions or layer distributions: "the power line located in the second area comprises a first wiring layer or a second wiring layer, and the power line and the first scanning line are set in different layers." Dividing a connecting branch line into sub-lines feeding multi-part nodes or multiple gates relies on standard routing adjustments within the knowledge of a person skilled in the art.
Splitting trace structures into parallel or multi-part sub-lines is a matter of routine design choice and a standard engineering practice employed to optimize signal integrity, reduce resistance, or meet physical clearance requirements. A person having ordinary skill in the art would have recognized this as a direct, predictable way to route connections to complex, split-gate transistor structures without requiring unexpected innovation
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JARRETT J STARK whose telephone number is (571)272-6005. The examiner can normally be reached 8-4 M-F.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Manno can be reached at 571-272-2339. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
JARRETT J. STARK
Primary Examiner
Art Unit 2822
7/2/2026
/JARRETT J STARK/ Primary Examiner, Art Unit 2898
Prosecution Insights