DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 3, 5-7, 9-15, and 24 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 3 recites the limitation "the fourth height". There is insufficient antecedent basis for this limitation in the claim.
Claim 24 recites the limitation "the fifth surface". There is insufficient antecedent basis for this limitation in the claim.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 5, 14, 15, 21, 22, 24, and 25 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Suh et al (U.S. Pub #2009/0146185).
With respect to claim 1, Suh teaches a semiconductor device, comprising:
a substrate (Fig. 8, 20);
a first nitride semiconductor layer (Fig. 8, 22) on the substrate;
a second nitride semiconductor layer (Fig. 8, 23’) on the first nitride semiconductor layer, the second nitride semiconductor layer comprising a first surface at a first height (Fig. 8, lower surface of 23’), a second surface at a second height (Fig. 8, upper surface of 23’), a third surface at a third height and between the first surface and the second surface (Fig. 8, bottom surface of trench in layer 23’), and a first side (Fig. 8, inclined trench surface of 23’) connecting the second surface and third surface and extending along a direction substantially parallel to the surface of the substrate;
a third nitride semiconductor layer (Fig. 8, 26 and Paragraph 52) on the third surface of the second nitride semiconductor layer; and
a dielectric layer (Fig. 8, 24) contacting the third nitride semiconductor layer and the first side of the second nitride semiconductor layer.
With respect to claim 2, Suh teaches the dielectric layer (Fig. 8, 24) contacts the third surface of the second nitride semiconductor layer (Fig. 8, bottom surface of trench in layer 23’).
With respect to claim 3, Suh teaches that the third nitride semiconductor layer comprises a fourth surface (Fig. 8, bottom surface of 26) at the third height and a fifth surface (Fig. 8, upper surface of 26) at the fourth height; wherein the fourth height is higher than the second height.
With respect to claim 5, Suh teaches that the third nitride semiconductor layer (Fig. 8, 26) comprises a second side (Fig. 8, vertical sides of 26) connecting the fourth surface and fifth surface of the third nitride semiconductor layer, and the dielectric layer (Fig. 8, 24) contacts the second side of the third nitride semiconductor layer.
With respect to claim 14, Suh teaches that wherein the projection of the fifth surface of the third nitride semiconductor layer (Fig. 8, 26) to the substrate overlaps the projection of the first side of the second nitride semiconductor layer (Fig. 8, edges of 26 and inclined portion of 23’).
With respect to claim 15, Suh teaches that the projection of the second side of the third nitride semiconductor layer to the substrate overlaps the projection of the first side of the second nitride semiconductor layer (Fig. 8, edges of 26 and inclined portion of 23’).
With respect to claim 21, Suh teaches a semiconductor device, comprising:
a substrate (Fig. 8, 20);
a first nitride semiconductor layer (Fig. 8, 21) on the substrate;
a second nitride semiconductor layer (Fig. 8, 23’) having a first surface at a first height (Fig. 8, bottom surface of 23’), a second surface at a second height (Fig. 8, upper surface of 23’), a third surface at a third height (Fig. 8, bottom surface of trench in layer 23’) and between the first surface and second surface, and a first side (Fig. 8, inclined trench surface of 23’) connecting the second surface and the second surface, wherein the first side extends along a direction substantially parallel to the surface of the substrate,
a third nitride semiconductor layer (Fig. 8, 26 and Paragraph 52) having a fourth surface (Fig. 8, bottom surface of 26) at the third height, a fifth surface (Fig. 8, upper surface of 26) at the fourth height, and a second side (Fig. 8, vertical sides of 26) connecting the fourth surface and fifth surface, wherein the second side comprises a portion substantially perpendicular to the surface of the substrate.
With respect to claim 22, Suh teaches that the projection of the portion of the second side to the normal of the substrate overlaps the projection of the first side of the second nitride semiconductor to the normal of the substrate; or, wherein the fourth height (Fig. 8, upper surface of 26) is higher than the second height (Fig. 8, upper surface of 23’).
With respect to claim 24, Suh teaches a dielectric (Fig. 8, 24) between the fifth surface of the third nitride semiconductor layer and the third surface of the second nitride semiconductor layer.
With respect to claim 25, Suh teaches a dielectric (Fig. 8, 24) between the first side of the second nitride semiconductor layer and the second side of the third nitride semiconductor layer.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 6, 7, 9-13, 16, and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Suh, in view of Jeon (U.S. Pub #2014/0021480).
With respect to claim 6, Suh does not teach that the second side extends along a direction substantially parallel to the surface of the substrate.
Jeon teaches that a second side of a third nitride semiconductor layer can include a portion that extends along a direction substantially parallel to the surface of the substrate (Figs. 1-3, the flat upper portion of third semiconductor material DP10 includes a flat portion on the underside that extends along a parallel direction to the substrate).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form the third nitride semiconductor material of Suh to have portions as taught by Jeon in order to epitaxially form a depletion region for the structure (Paragraph 85-86).
With respect to claim 7, Jeon teaches that the projection of the second side of the third nitride semiconductor layer (Figs. 1-3, the flat upper portion of third semiconductor material DP10) to the substrate non- overlaps the projection of the fourth surface (Fig. 1-3, bottom surface of DP10 that contacts CS10) of the third nitride semiconductor layer to the substrate;
or, wherein the projection of the second side of the third nitride semiconductor layer to the substrate overlaps the projection of the fifth surface of the third nitride semiconductor layer to the substrate.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form the third nitride semiconductor material of Suh to have portions as taught by Jeon in order to epitaxially form a depletion region for the structure (Paragraph 85-86).
With respect to claim 9, Suh does not teach that the second side comprises a first portion substantially perpendicular to the surface of the substrate and a second portion extending along a direction substantially parallel to the surface of the substrate.
Jeon teaches a second side comprises a first portion substantially perpendicular to the surface of the substrate and a second portion extending along a direction substantially parallel to the surface of the substrate (Figs. 1-3, the flat upper portion of third semiconductor material DP10).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form the third nitride semiconductor material of Suh to have portions as taught by Jeon in order to epitaxially form a depletion region for the structure (Paragraph 85-86).
With respect to claim 10, Jeon teaches that the projection of the second portion (Figs. 1-3, top portion DP10 extending horizontally) to the substrate non-overlaps the projection of the fourth surface (Fig. 1-3, bottom surface of DP10) of the third nitride semiconductor layer to the substrate.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form the third nitride semiconductor material of Suh to have portions as taught by Jeon in order to epitaxially form a depletion region for the structure (Paragraph 85-86).
With respect to claim 11, Jeon teaches the projection of the second portion (Figs. 1-3, top portion DP10 extending horizontally) to the substrate overlaps the projection of the fifth surface (Fig. 1-3, overall upper surface of DP10) of the third nitride semiconductor layer to the substrate.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form the third nitride semiconductor material of Suh to have portions as taught by Jeon in order to epitaxially form a depletion region for the structure (Paragraph 85-86).
With respect to claim 12, Jeon teaches that the second side further comprises a third portion (Figs. 1-3, outermost vertical sidewalls of DP10) substantially perpendicular to the surface of the substrate, wherein the second portion is between the first portion and the third portion.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form the third nitride semiconductor material of Suh to have portions as taught by Jeon in order to epitaxially form a depletion region for the structure (Paragraph 85-86).
With respect to claim 13, Suh does not teach that the projection of the fifth surface of the third nitride semiconductor layer to the substrate overlaps the projection of the second surface of the second nitride semiconductor layer.
Jeon teaches that the projection of the fifth surface of the third nitride semiconductor layer (Figs. 1-3, the flat upper portion of third semiconductor material DP10) to the substrate overlaps the projection of the second surface (Fig. 1-3, inclined surface of CS10) of the second nitride semiconductor layer.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form the third nitride semiconductor material of Suh to have portions as taught by Jeon in order to epitaxially form a depletion region for the structure (Paragraph 85-86).
With respect to claim 16, Suh teaches a method for fabricating a semiconductor device, comprising:
providing a substrate (Fig. 8, 20);
forming a first nitride semiconductor layer (Fig. 8, 22) on the substrate;
forming a second nitride semiconductor layer (Fig. 8, 23’) on the first nitride semiconductor layer, wherein the second nitride semiconductor layer comprises a first surface at a first height (Fig. 8, bottom surface of 23’) and a second surface at a second height (Fig. 8, upper surface of 23’);
forming a third surface at a third height (Fig. 8, bottom surface of trench in layer 23’) and between the first surface and the second surface, and a first side (Fig. 8, inclined trench surface of 23’) connecting the second surface and third surface, wherein the first side extends along a direction substantially parallel to the surface of the substrate;
forming a dielectric layer (Fig. 8, 24) on the second nitride semiconductor layer;
exposing a portion of the third surface of the second nitride semiconductor layer; and
forming a third nitride semiconductor layer (Fig. 8, 26 and Paragraph 52) on the third surface of the second nitride semiconductor layer, wherein the dielectric layer contacts the third nitride semiconductor layer and the first side of the second nitride semiconductor layer.
Suh does not teach etching the second surface of the second nitride semiconductor layer to form a third surface at a third height.
Jeon teaches etching a second surface of a second nitride semiconductor layer to form a third surface at a third height (Paragraph 116).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to etch the second surface of Suh as taught by Jeon in order to achieve the predictable result of forming the trench in the second nitride layer (Paragraph 116).
With respect to claim 17, Suh teaches that the dielectric layer contacts the third surface of the second nitride semiconductor layer; or,
wherein the third nitride semiconductor layer comprises a fourth surface (Fig. 8, bottom surface of 26) at the third height and a fifth surface at a fourth height (Fig. 8, top surface of 26);
wherein the fourth height is higher than the second height (Fig. 8, top surface of 23’).
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Suh and Jeon, in view of Liu et al (U.S. Pub #2021/0320199).
With respect to claim 20, Suh does not teach removing a portion of the second nitride semiconductor layer to form a sixth surface of the second nitride semiconductor layer, wherein the sixth surface is at a fifth height that is higher than the first height.
Liu teaches removing a portion of a second nitride semiconductor layer (Fig. 1, 5) to form a sixth surface (Fig. 1, surface for the contact of 8 or 9) of the second nitride semiconductor layer, wherein the sixth surface is at a fifth height that is higher than a first height (Fig. 1, bottom surface of 5).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to remove a portion of the second nitride semiconductor layer of Suh to form a sixth surface as taught by Liu in order to achieve the predictable result of forming an ohmic contact surface for the source or drain electrodes (Paragraph 24).
Conclusion
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/BENJAMIN P SANDVIK/Primary Examiner, Art Unit 2812
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