Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 4/17/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-8 and 10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Son (US 20210066421 A1)
Regarding claim 1, Son discloses an array substrate (Fig. 19), comprising:
a base substrate (101), wherein the base substrate is provided with a first region (AR1) and a second region (AR1) which are juxtaposed (horizontally “juxtaposed”, See annotated figure for direction designation);
a first transistor (within AR1; [0083]: “transistor region”), wherein the first transistor is located in the first region and is provided with a first active layer (105), and the first active layer is low temperature polycrystalline silicon (LTPS) ([0093]: “polycrystalline silicon”. Note: [0102]: “high temperature activation” implies there is a lesser temperature state at some point during the formation of the resultant active layer. Thus, this active layer is “low temperature” within the breadth of the claim as written.);
a second transistor (within AR2; [0083]: “transistor region”), wherein the second transistor is located in the second region and is provided with a second active layer (135), and the second active layer is a metal oxide semiconductor ([0103]: “oxide semiconductor…IGZO”);
a first light-shielding layer (104 and including 112_2 grouped with it; [0084]: “light-shielding”), wherein the first light-shielding layer is arranged right below (vertically “below”, See annotated figure for direction designation. Note: “right below” is interpreted here consistent with Applicant’s disclosure: Fig. 1: layer 052.) the second active layer, and at least an interlayer dielectric layer (GI1 or ILD1) is arranged between (vertically “between”) the first light-shielding layer and the second active layer; and
a second light-shielding layer (163; [0124]: “light shielding”), wherein the second light-shielding layer is arranged right above (vertically “above”, See annotated figure for direction designation. Note: “right above” is interpreted here consistent with Applicant’s disclosure: Fig. 1: layer 162.) the second active layer, and a planarization layer (VIA1) and a fifth insulating layer (ILD2) are arranged between (vertically “between”) the second light-shielding layer and the second active layer.
Illustrated below is a marked and annotated figure of Fig. 19 of Son.
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Regarding claim 2, Son discloses the array substrate according to claim 1 (Fig. 19), wherein a buffer layer (103; [0084]: “buffer layer”) is arranged between (vertically “between”) the first active layer and an upper surface of the base substrate; the first transistor is further provided with a first gate layer (111); a first insulating layer (GI1) is arranged between (vertically “between”) the first gate layer and an upper surface of the first active layer; and a source-drain electrode layer (151/152) of the first transistor is electrically connected to two ends of the first active layer (ends 105a/105b) through two through holes (CNT1/CNT2) respectively.
Regarding claim 3, Son discloses the array substrate according to claim 2 (Fig. 19), wherein the second transistor is further provided with a second gate layer (112_2; [0185]: “metal”) and a third gate layer (142); a third insulating layer (ILD1) is arranged between (vertically “between”) the second gate layer and a lower surface of the second active layer; a fourth insulating layer (GI2) is arranged between (vertically “between”) the third gate layer and an upper surface of the second active layer; and a source-drain electrode layer (153/154) of the second transistor is electrically connected to two ends of the second active layer (ends 135a/135b) through two through holes (CNT3/CNT4).
Regarding claim 4, Son discloses the array substrate according to claim 3 (Fig. 19), wherein a width (horizontal “width”) of the first light-shielding layer and a width (horizontal “width”) of the second light-shielding layer are not less than (See dashed reference lines) a width (horizontal “width”) of the second active layer.
Regarding claim 5, Son discloses the array substrate according to claim 4 (Fig. 19), wherein the second light-shielding layer is formed by partially etching ([0167]: “etched”) an organic light emitting diode (OLED) ([0130]: “light-emitting…organic material”) anode layer (layer 160 includes piece 161, which is directly shorted to anode layer ANO, thus it is an “anode layer”).
Regarding claim 6, Son discloses the array substrate according to claim 5 (Fig. 19), wherein the first light-shielding layer (portion 112_2 of the collection) is formed by partially etching the first gate layer (Fig. 19 shows 112_2 is grouped with gate 111 in the group 110; [0180]: “mask”).
Regarding claim 7, Son discloses the array substrate according to claim 5 (Fig. 19), wherein the first light- shielding layer is the second gate layer (this is the designation cited above).
Regarding claim 8, Son discloses the method for manufacturing the array substrate according to claim 6 (Fig. 19), comprising: depositing a metal layer ([0098]: “layer 110 is disposed…molybdenum”) on an upper surface of the first insulating layer ([0098]: “on…GI1”); and partially etching the metal layer (Fig. 19 shows 112_2 is grouped with gate 111 in the group 110; [0180]: “mask”) to obtain the first gate layer located in the first region and the first light-shielding layer located in the second region.
Regarding claim 10, Son discloses a display apparatus ([0183]: “a display device”), comprising the array substrate according to claim 1 (Fig. 19).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Rejection Note: Italicized claim limitations indicate limitations that are not explicitly disclosed in the primary reference (or combination of references), but are disclosed or rendered obvious by secondary references or remarks.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Son as applied to claim 7 above, and further in view of Kim (US 20190214447 A1, from IDS).
Regarding claim 9, Son discloses a method for manufacturing the array substrate according to claim 7 (Fig. 19), comprising: depositing a second insulating layer (ILD1) after forming the first gate layer of the first transistor, wherein the second insulating layer further extends (horizontally “extends”) to the second region of the base substrate; depositing a metal layer (140; [0110]: “layer 140 is disposed…molybdenum”) on an upper surface of the second insulating layer (indirectly “on”); and partially etching the metal layer ([]: “”) to obtain a capacitor upper electrode layer located in the first region ([0110]: “the second electrode 141 of the capacitor Cst”) and the first light-shielding layer located in the second region.
Son separately teaches obtaining “a capacitor upper electrode layer” and “the first light shielding layer”, but fails to teach obtaining these layers at the claimed method sequence “after” because the “first light-shielding layer” is already obtained at the arrangement of Fig. 19: 104/112_2 . Therefore, Son fails to teach “partially etching the metal layer to obtain a capacitor upper electrode layer located in the first region and the first light-shielding layer located in the second region”.
Kim teaches depositing a second insulating layer (Fig. 8A: ILD1) after forming the first gate layer (G2) of the first transistor (Driving TFT), wherein the second insulating layer further extends to the second region (Switching TFT region) of the base substrate (Glass or Flexible Substrate); depositing a metal layer on an upper surface of the second insulating layer; and partially etching the metal layer (810/760; [0055]: “light shields 810/820 are formed from a metal material” and [0063]: “source metals”) to obtain a capacitor upper electrode layer ([0063]: “storage capacitor”) located in the first region (Driving TFT region) and the first light-shielding layer (810) located in the second region.
Modifying the method (of Son) by incorporating the alternative sequence and arrangement of parts (of Kim) “to obtain… the first light-shielding layer” would arrive at the claimed method sequence and arrangement of parts. A person of ordinary skill in the art before the effective filing date would have had a reasonable expectation of success doing so because Kim teaches the claimed shielding layer sequence and arrangement may be chosen as a variation among other sequences and arrangements (alternative sequence/arrangement Fig. 8B). Therefore, it would have been obvious to have the claimed method configuration because it is a known sequence and arrangement found elsewhere in the prior art for substantially similar structures. MPEP 2144.04 (VI)C).
Illustrated below is Fig. 8A of Kim.
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Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to WILLIAM H ANDERSON whose telephone number is (571)272-2534. The examiner can normally be reached Monday-Friday, 8:00-5:00.
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/WILLIAM H ANDERSON/ Examiner, Art Unit 2817
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