DETAILED ACTION
This Office action responds to the application filed on 04/17/2024.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for a rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Election/Restrictions
Applicant’s election of Species 1, reading on figures 1-8, in the reply filed on 09/28/2026, is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)). The applicant indicates that claims 1-3, 7, 9, 10, & 16 read on the elected species. The examiner agrees. Accordingly, claims 4-6, 8, & 11-15 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim.
Claim Rejections - 35 USC § 102 & 103
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 3, 9, 10, & 16 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Hayaski (US 20100327383).
Regarding Claim 1, Hayasaki shows a semiconductor device, comprising:
a board silicon 10 (see, e.g., para.0028);
a silicon oxide film 23 (see, e.g., para.0029, para.0035) stacked on the board silicon;
an inter-wiring-layer film 25 (see, e.g., para.0030) having an internal electrode 26b stacked on the silicon oxide film;
a through-hole (see, e.g., fig. 2, para.0034) forming
a stepped hole with a larger-diameter hole extending from the board silicon to the silicon oxide film (extending vertically from 10 to 23, see, e.g., annotated figure 1)
and a smaller-diameter hole extending from the silicon oxide film to the internal electrode (extending vertically from 23 to 26b, see, e.g., annotated figure 1);
an interlayer dielectric film 35 (see, e.g., para.0034) stacked on a circumferential side surface of the larger-diameter hole and the board silicon;
and a redistribution layer 36 & 37 (see, e.g., para.0034) formed on an inner peripheral surface of the through-hole and the interlayer dielectric film and connected to the internal electrode.
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Annotated Figure 1
Regarding Claim 2, Hayasaki shows the semiconductor device according to claim 1,
wherein a circumferential side surface of the smaller-diameter hole is held in close contact with a through-portion of the silicon oxide film (opening of 23 is near side surface of the smaller-diameter hole, see, e.g., annotated figure 1).
Regarding Claim 3, Hayasaki shows the semiconductor device according to claim 1,
wherein the internal electrode is formed of a copper film (see, e.g., para.0033).
Regarding Claim 9, Hayasaki shows the semiconductor device according to claim 1,
wherein the redistribution layer 36 & 37 has a solder bump 18 (see, e.g., para.0062) provided at an opening of the through-hole.
Regarding Claim 10, Hayasaki shows the semiconductor device according to claim 1,
wherein the semiconductor device is a solid-state imaging device (Hayasaki shows a solid-state imaging device as a camera module, see, e.g., para.0019).
Regarding Claim 16, Hayasaki shows an electronic apparatus, comprising
a semiconductor device including
a board silicon 10 (see, e.g., para.0028),
a silicon oxide film 23 (see, e.g., para.0029, para.0035) stacked on the board silicon,
an inter-wiring-layer film 25 (see, e.g., para.0030) having an internal electrode 26b stacked on the silicon oxide film,
a through-hole (see, e.g., fig. 2, para.0034) forming
a stepped hole with a larger-diameter hole extending from the board silicon to the silicon oxide film (extending vertically from 10 to 23, see, e.g., annotated figure 1)
and a smaller-diameter hole extending from the silicon oxide film to the internal electrode (extending vertically from 23 to 26b, see, e.g., annotated figure 1),
an interlayer dielectric film 35 (see, e.g., para.0034) stacked on a circumferential side surface of the larger-diameter hole and the board silicon,
and a redistribution layer 36 & 37 (see, e.g., para.0034) that is formed on an inner peripheral surface of the through-hole and the interlayer dielectric film and is connected to the internal electrode.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Hayasaki (US 20100327383) in view of Mitsuhashi (US 20140291841).
Regarding Claim 7, Hayasaki shows the semiconductor device according to claim 1,
Hayasaki, however, fails to show
wherein a connection surface between the smaller-diameter hole and the internal electrode is formed in a circular shape.
Mitsuhashi, in a device similar to Hayasaki, shows
wherein a connection surface between the smaller-diameter hole and the internal electrode is formed in a circular shape.
Mitsuhashi (see, e.g., fig. 4, fig. 5L, para.0076, para.0105) states the configuration of the connection surface formed in a circular shape allow for contact between electrode 17 and the pad 33. The electrode 17 and the pad 33 function similarly to the redistribution layer and the internal electrode of Claim 1, respectively. Mitsuhashi states the configuration would provide a reliable connection. The configuration of Mitsuhashi is incorporated into the device of Hayasaki
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to incorporate the configuration of Mitsuhashi in the device of Hayasaki to provide a reliable connection.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to FERNANDO JOSE RAMOS-DIAZ whose telephone number is (571) 270-5855. The examiner can normally be reached Mon-Fri 8am-5pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven Loke can be reached on 571-272-1657. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/FERNANDO JOSE RAMOS-DIAZ/Examiner, Art Unit 2818
/STEVEN H LOKE/Supervisory Patent Examiner, Art Unit 2818
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