Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This Office Action is in response to Applicant’s Response to Election/Restriction Requirement received on August 19, 2026, regarding the application filed April 18, 2024.
Election/Restrictions
Applicant’s election without traverse of Group I, corresponding to claims 1-8, in the reply filed on August 19, 2026 is acknowledged. Claims 9-20 have been withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. This restriction requirement has been finalized.
Claims 1-20 are pending, with claims 9-20 currently withdrawn from consideration.
Priority
This application is a National Stage Entry of PCT International Application No. PCT/ KR2022/ 010184, filed on July 13, 2022, and which claims priority from and the benefit of Korean Patent Application 10-2021-0154047, filed with the Korean Intellectual Property Office on November 10, 2021. Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on April 18, 2024, July 24, 2025, and November 21, 2025 have been placed in the application file and are being considered by the examiner.
Drawings
The drawings filed with the application on April 18, 2024 are accepted.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 6 and 7 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Roberts et al., US 2018/0323199 A1 (hereinafter Roberts).
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Regarding claim 6, Roberts discloses: A three-dimensional memory array (Roberts, FIGs. 1, 4, memory array 10) including isolated insulating layers (Roberts, FIGs. 1, 4, insulator material 49, [0076]) and memory cell layers (Roberts, FIGs. 1, 4, memory cell tiers 14, [0076]) alternately stacked in a vertical direction (Roberts, see FIGs. 1, 4, [0076]) and individually constructing a transistor (Roberts, FIGs. 1, 4, transistor 25, [0061; 0067]) and a capacitor (Roberts, FIGs. 1, 4, capacitor 34, [0061; 0065]), wherein the capacitor includes:
a first electrode formed in a horizontal direction in each of the memory cell layers (Roberts, FIGs. 1 and 22 show first electrode 46 [the first electrode] formed in a horizontal direction in each of memory cell tiers 14 [the memory cell layers], [0065]);
a second electrode extending in the vertical direction and protruding in the horizontal direction in each of the isolated insulating layers (Roberts, FIGs. 1 and 22 shows second electrode 48 [the second electrode] extending in the vertical direction and protruding in the horizontal direction in each of the insulator material 49 [the isolated insulating layers], [0065]); and
a capacitor dielectric film formed to be in contact with the second electrode (Roberts, FIGs. 1, 22 show capacitor insulator 50 [the capacitor dielectric film] formed to be in contact with second electrode 48 [the second electrode], [0065-0080]),
wherein the capacitor dielectric film is formed to be in contact with the second electrode and cover a top surface, a side surface, and a bottom surface of the first electrode (Roberts, FIGs. 1, 22 show capacitor insulator 50 [the capacitor dielectric film] formed to be in contact with second electrode 48 [the second electrode] and covering a top surface, a side surface, and a bottom surface of first electrode 46 [the first electrode]).
Regarding claim 7, Roberts discloses: The three-dimensional memory array of claim 6, wherein the first electrode (Roberts, FIGs. 1 and 22, first electrode 46) is electrically connected to a source among the source and a drain included in the transistor in each of the memory cell layers (Roberts, FIG. 1 shows first electrode 46 [the first electrode] connected to first source/drain region 20 [the source] in transistor 25 in each of memory cell tiers 14 [the transistor in each of the memory cell layers], “First electrode 46 [the first electrode] is electrically coupled [electrically connected] … to first source/drain region 20 [the source],” [0065]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 4 and 5 are rejected under 35 U.S.C. 103 as being unpatentable over Roberts et al., US 2018/0323199 A1 (hereinafter Roberts) in view of Applicant’s Admitted Prior Art (hereinafter APA).
The Background section of Applicant’s specification discusses prior art methods for implementing three-dimensional memory at paragraphs [0002-0018]. This portion of Applicant’s specification is relied upon in the following rejection and will be referred to as Applicant’s Admitted Prior Art (hereinafter APA). See MPEP 2129 regarding admissions by Applicant as prior art.
Regarding claim 1, Roberts discloses: A three-dimensional memory array including isolated insulating layers (Roberts, FIGs. 1, 4, insulator material 49, [0076]) and memory cell layers (Roberts, FIGs. 1, 4, memory cell tiers 14, [0076]) alternately stacked in a vertical direction (Roberts, see FIGs. 1, 4, [0076]) and individually constructing a transistor (Roberts, FIGs. 1, 4, transistor 25, [0061; 0067]) and a capacitor (Roberts, FIGs. 1, 4, capacitor 34, [0061; 0065]), wherein the transistor includes:
a gate film (Roberts, FIGs. 1, 4, gate 26/27 [0062]) extending in the vertical direction and protruding in a horizontal direction from each of the isolated insulating layers (Roberts, FIGs. 1, 4, show gate 26/27 [the gate film] extending in the vertical direction and protruding in a horizontal direction from each of insulator material 49 [the isolated insulating layers], [0062]);
a channel (Roberts, FIGs. 1, 4, channel region 24, [0061]) surrounding at least partial side surface of the gate film in each of the memory cell layers (Roberts, FIGs. 1, 4, show channel region 24 [the channel] surrounding at least partial side surface of gate 26/27 [the gate film] in each of memory cell tiers 12/14 [the memory cell layers], [0062]); and
a source and a drain (Roberts, FIGs. 1, 4, source/drain regions 20 and 22, [0061]) disposed on both sides of the gate film (Roberts, FIGs. 1, 4, source/drain regions 20 and 22 [the source and the drain] shown disposed on both sides of gate 26/27 [the gate film], [0061]) whose at least partial side surface is surrounded by the channel in each of the memory cell layers (Roberts, FIGs. 1, 3, 4, source/drain regions 20 and 22 [the source and the drain] shown surrounded by channel region 24 [the channel] in each of memory cell tiers 12/14 [the memory cell layers], [0061-0063]),
wherein the channel, and the source and the drain are made of semiconductor materials (Roberts, [0061])
Examiner notes that the claim recites “the channel” and “the source and the drain” as two distinct structures. Although Roberts discloses that the channel, and the source and the drain are made of semiconductor materials, Roberts is silent regarding that they are with different doping concentrations, respectively.
However, APA teaches, as stated in the Background section of Applicant’s disclosure, that it was known in the art before the effective filing date of the claimed invention that “by including the source and the drain, and the channel formed with different doping concentrations, a performance and a regulation ability of the transistor may be improved,” (APA, [0008]). APA describes the recognized difficulty of adjusting impurity doping to adjust the actual performance of the transistor (APA, [0009]), and the “need to propose detailed technology on how to form the source and the drain, and the channel with the different doping concentrations in the three-dimensional DRAM” (APA, [0010]). The market pressure to solve the problem was known in the art and one of ordinary skill in the art would have been motivated to pursue the finite number of predictable potential solutions.
Therefore, one of ordinary skill in the art would have been motivated to solve this problem, and it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to apply the teachings of APA to the teachings of Roberts with predictable results and without undue experimentation, insofar as selecting different doping concentrations for the channel, and the source and the drain. The motivation for doing so would be, as was known in the art and as expressly recognized by APA, to improve device performance (APA, [0008]).
Regarding claim 2, Roberts in view of APA teaches: The three-dimensional memory array of claim 1, wherein the semiconductor material forming the channel (Roberts, FIGs. 1, 4, channel region 24, [0061]) and the semiconductor material forming the source and the drain (Roberts, FIGs. 1, 4, source/drain regions 20 and 22, [0061]) are doped with different types of impurities. APA teaches that the semiconductor material forming the channel is “made of silicon with low p-type impurity concentration,” (APA, [0007]); the semiconductor material forming the source and the drain is “made of silicon with high n-type impurity concentration,” (APA, [0007]), i.e., doped with different types of impurities. Furthermore, APA teaches that “by including the source and the drain, and the channel formed with different doping concentrations, a performance and a regulation ability of the transistor may be improved,” (APA, [0008])).
Regarding claim 4, Roberts in view of APA teaches: The three-dimensional memory array of claim 1, further comprising: an ohmic film (Roberts, FIG. 1, conductive material 58, [0002; 0067]) for reducing a contact resistance between the source and the drain and at least one of a bit line in contact with the source and the drain (Roberts, FIG. 1 shows conductive material 58 [the ohmic film] between source/drain regions 20 and 22 [the source and the drain] and sense-line structure 56 [the bit line], [0002; 0067]; “sense line [the bit line] is electrically coupled … to multiple of the second source/drain regions [the source and the drain],” [0067])
The claim language for reducing a contact resistance has not been given full patentable weight because it is merely descriptive of an intended use or function.
When a claim requires selection of an element from a list of alternatives, the prior art teaches the element if one of the alternatives is taught by the prior art. See, e.g., Fresenius USA, Inc. v. Baxter Int’l, Inc., 582 F.3d 1288, 1298, 92 USPQ2d 1163, 1171 (Fed. Cir. 2009). The alternative elements taught by Roberts include one or more of Applicant’s claimed alternative elements, for example: an ohmic film between the source and the drain and a bit line in contact with the source and the drain.
Regarding claim 5, Roberts in view of APA teaches: The three-dimensional memory array of claim 1, further comprising: a gate insulating film (Roberts, FIG. 1, gate insulator 28, [0062]) interposed between the gate film and the channel (Roberts, FIG. 1 shows gate insulator 28 [the gate insulating film] interposed between gate 26/27 [the gate film] and channel region 24 [the channel], [0062]).
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Roberts in view of APA, as applied to claim 1 above, and further in view of Wang et al., US 2007/0187725 A1 (hereinafter Wang).
Regarding claim 3, Roberts in view of APA teaches: The three-dimensional memory array of claim 1. Roberts in view of APA is silent regarding: a counter doping layer disposed in portions of the source and the drain in contact with the channel, wherein the counter doping layer allows the channel to be easily formed with the semiconductor material having the different doping concentration from the semiconductor material forming the source and the drain.
While features of a device may be recited either structurally or functionally, claims directed to a device must be distinguished from the prior art in terms of structure rather than function or intended use. See MPEP 2114; see also MPEP 2103(C), generally. The intended function or use of a claimed structure is given patentable weight only so far as the structure is capable of performing that function or capable of the intended use. This capability is compared against the prior art, as opposed to prior teachings of the particular function or use. The claim language wherein the counter doping layer allows the channel to be easily formed with the semiconductor material having the different doping concentration from the semiconductor material forming the source and the drain has not been given full patentable weight because it is merely descriptive of an intended use or function.
Wang, in the same field of endeavor, teaches the advantages of forming “transistors with counter-doped channels of different dopants,” (Wang, [0019]). Wang teaches that counter-doped channel material provides enhanced transistor performance (Wang, [0012]). Wang teaches: a counter doping layer (Wang, FIG. 12, counter-doped channel material 214, [0064]) disposed in portions of the source and the drain in contact with the channel (Wang, FIG. 12 shows counter-doped channel material 214 [the counter doping layer] disposed at edge portions of the source and drain regions 240, 242, 244, 246 [the source and the drain] in contact with doped channel material 210 [the channel], [0063-0064]).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Roberts in view of APA with the teachings of Wang, arriving at Applicant’s claimed invention with predictable results and without undue experimentation. The motivation for doing so would be, as expressly recognized by Wang, to increase performance and allow adjustment of threshold voltages (Wang, [0011]), thereby improving device performance and reliability.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Roberts, as applied to claim 6 above, in view of Yoon, US 2007/0007656 A1 (hereinafter Yoon).
Regarding claim 8, Roberts discloses: The three-dimensional memory array of claim 7, wherein the first electrode (Roberts, FIGs. 1 and 22, first electrode 46) is in contact with the source (Roberts, FIG. 1 shows first electrode 46 [the first electrode] connected to first source/drain region 20 [the source])
Roberts is silent regarding: an ohmic film disposed between the first electrode and the source to reduce a contact resistance. However, use of an ohmic film to reduce contact resistance between an electrode and a contact was known in the art before the effective filing date of the claimed invention. For example, Yoon, in the same field of endeavor, teaches: a semiconductor device including an ohmic film made of titanium or titanium nitride formed on a contact to reduce an ohmic resistance, i.e., to reduce a contact resistance (Yoon, “the titanium film may operate as an ohmic film capable of reducing an ohmic resistance,” [0048-0049]).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Roberts with the teachings of Yoon, arriving at Applicant’s claimed invention with predictable results and without undue experimentation. The motivation for doing so would be, as expressly recognized by Yoon, to reduce resistance, thereby improving device performance and reliability.
Conclusion
The prior art made of record and not relied upon is considered pertinent to Applicant’s disclosure. The cited prior art discloses similar materials, devices, and methods.
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/D.L.N./Examiner, Art Unit 2899
/Brent A. Fairbanks/Supervisory Patent Examiner, Art Unit 2899
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