DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
As per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
In responding to this Office action, the applicant is requested to include specific references (figures, paragraphs, lines, etc.) to the drawings/specification of the present application and/or the cited prior arts that clearly support any amendments/arguments presented in the response, to facilitate consideration of the amendments/arguments.
Response to Amendment
The amendment filed March 3, 2026 has been entered. Claims 1, and 3-14 remain pending in this application. Claims 6-14 drawn to non-elected invention have been withdrawn. Claim 2 cancelled at applicant’s request. Claims 1, 3, and 5 have been amended, adding no new matter. No claims have been added.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1 and 3 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by US 2005/0276120 A1 to Ed Hsia, et al. (hereafter Hsia).
Regarding Claim 1, Hsia discloses a multi-level implementing method in a 3D flash memory (Disclosing a multi-level method for programming 3D flash memory: Hsia, ¶[0013]), the method comprising:
securing a threshold voltage distribution region (Distributing voltage thresholds within a bounded region: Hsia, ¶[0034])
by narrowing a distribution (Forming compact voltage threshold distributions: Hsia, ¶[0032]) of an erase threshold voltage (Specifically forming narrow erase distributions: Hsia, ¶[0030])
during an erase operation of the 3D flash memory (Disclosing the process of narrow erase voltage thresholds in the context of an erase operation: Hsia, Figure 4A); and
setting multi-level program threshold voltages in the secured threshold voltage distribution region (Setting the remaining voltage thresholds evenly in the available voltage distribution region: Hsia, ¶[0034]),
wherein the securing includes:
applying an initial erase voltage to a selected word line (Disclosing an initial erase pulse: Hsia, ¶[0043])
corresponding to a memory cell that is a target of the erase operation among a plurality of word lines included in the 3D flash memory (Applying the initial erase pulse to an array or portions of an array as the target of the erase operation: Hsia, ¶[0044]);
applying a read voltage to the selected word line (Disclosing ‘testing’ – reading – the erased memory cells: Hsia¶[0044]); and
applying an additional erase voltage to the selected word line (Applying additional erase pulses to the targeted memory cells: Hsia, ¶[0044]).
Regarding Amended Claim 3, Hsia discloses the method of claim 1, wherein
the applying of the read voltage and the applying of the additional erase voltage are sequentially repeated at least once or more (Testing and re-applying an erase voltage sequentially: Hsia, ¶[0044]; Note, while the first phase of the erasing operation may consist of only one or two erase pulses, Hsia further describes a second phase of the erase operation comprising additional erase pulses: Hsia, ¶[0047]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 4-5 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2005/0276120 A1 to Ed Hsia, et al. (hereafter Hsia) in view of US 7,057,936 B2 to Toshitake Yaegashi, et al. (hereafter Yaegashi).
Regarding Claim 4, Hsia discloses the method of claim 3, but fails to disclose the further limitations of Claim 4. Yaegashi, however, discloses an erase operation as in Claim 3, wherein
the additional erase voltage decreases as the applying of the read voltage and the applying of the additional erase voltage are sequentially repeated (Disclosing a series of erase pulses where the erase voltage decreases as each pulse is repeated: Yaegashi, Figure 36A).
Yaegashi teaches reducing the magnitude of the erase voltage pulse with subsequent erase pulses provides a narrow erase threshold distribution while maintaining high reliability (Yaegashi, col.32:32-37). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to combine the decreasing voltage pulses of Yaegashi with the narrow voltage threshold distribution method of Hsia, with a reasonable expectation of success. Both inventions are well known in the field of narrowing memory cell threshold distributions and the combination of known inventions with predictable results is obvious and not patentable.
Regarding Amended Claim 5, Hsia discloses the method of claim 1, but fails to disclose the further limitations of Claim 5. Yaegashi, however, discloses an erase operation as in Claim 2, wherein
the additional erase voltage has a value smaller than the initial erase voltage (Disclosing a series of erase pulses where the erase voltage decreases as each pulse is repeated: Yaegashi, Figure 36A).
Yaegashi teaches reducing the magnitude of the erase voltage pulse with subsequent erase pulses provides a narrow erase threshold distribution while maintaining high reliability (Yaegashi, col.32:32-37). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to combine the decreasing voltage pulses of Yaegashi with the narrow voltage threshold distribution method of Hsia, with a reasonable expectation of success. Both inventions are well known in the field of narrowing memory cell threshold distributions and the combination of known inventions with predictable results is obvious and not patentable.
Response to Arguments
Applicant's arguments filed March 3, 2026 have been fully considered but they are not persuasive.
Applicant argues Hsia fails to disclose “applying a read voltage to the selected word line,” as evidenced by the failure of Hsia to disclose a read voltage or a word line. This argument is unpersuasive. The applicant is entitled to be his or her own lexicographer, a privilege similarly extended to all applicants. Just because Hsia fails to use the precise words “word line” or “read voltage” does not mean it necessarily fails to disclose the concepts represented by those words. In fact, Hsia does use the word “wordline” in ¶8, but as one word, not two.
More significantly, Hsia discloses applying a verification voltage to memory cells in an array in paragraphs 9 and 45-48, although using the term ‘testing’ instead of verifying in paragraph 47. A verification is a read and is performed in the same manner. A test voltage is applied to a word line and circuitry checks the state of the individual bitlines. When discussing applying a read voltage, even the present application labels it Vverify (Specification, ¶53). Similar logic applies to the argument that Hsia fails to disclose applying an erase voltage to a selected wordline. Applying an erase voltage to specific wordlines is inherent in performing an erase operation.
Although unpersuasive, Applicant's response is considered to be a bona fide attempt at a response and is being accepted as a complete response.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 20080049521 A1 to Rino Micheloni, et al.: Disclosing compacting the voltage threshold of erased memory cells thereby increasing the allowable cell programming range.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/CHRISTOPHER LANE REECE/Examiner, Art Unit 2824
/JEROME LEBOEUF/Primary Examiner, Art Unit 2824 - 03/26/2026