DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
As per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
In responding to this Office action, the applicant is requested to include specific references (figures, paragraphs, lines, etc.) to the drawings/specification of the present application and/or the cited prior arts that clearly support any amendments/arguments presented in the response, to facilitate consideration of the amendments/arguments.
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on June 29, 2026 has been entered.
Response to Amendment
The amendment filed June 29, 2026 has been entered. Claims 1 and 3-14 remain pending in this application. Claims 6-14 drawn to non-elected invention have been withdrawn. Claim 2 previously cancelled at applicant’s request. Claims 1 and 3-5 have been amended. No claims have been added. No new matter has been added.
Specification
Applicant is reminded of the proper content of an abstract of the disclosure.
A patent abstract is a concise statement of the technical disclosure of the patent and should include that which is new in the art to which the invention pertains. The abstract should not refer to purported merits or speculative applications of the invention and should not compare the invention with the prior art.
If the patent is of a basic nature, the entire technical disclosure may be new in the art, and the abstract should be directed to the entire disclosure. If the patent is in the nature of an improvement in an old apparatus, process, product, or composition, the abstract should include the technical disclosure of the improvement. The abstract should also mention by way of example any preferred modifications or alternatives.
Where applicable, the abstract should include the following: (1) if a machine or apparatus, its organization and operation; (2) if an article, its method of making; (3) if a chemical compound, its identity and use; (4) if a mixture, its ingredients; (5) if a process, the steps.
Extensive mechanical and design details of an apparatus should not be included in the abstract. The abstract should be in narrative form and generally limited to a single paragraph within the range of 50 to 150 words in length.
See MPEP § 608.01(b) for guidelines for the preparation of patent abstracts.
As submitted, the abstract reads, in its entirety, “Disclosed are a 3D flash memory and an operating method thereof.”
The abstract of the disclosure is objected to because a single sentence that only names the field of the invention, and recites neither the problem addressed nor the solution proposed, does not meet the requirements of MPEP §608.01(b). It is, in substance, an omitted abstract. A corrected abstract of the disclosure is required and must be presented on a separate sheet, apart from any other text. See MPEP § 608.01(b).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1 and 3-4 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2005/0276120 A1 to Ed Hsia, et al. (hereafter Hsia) in view of US 2013/0107628 A1 to Yingda Dong, et al. (hereafter Dong) and further in view of US 7,522,457 B2 to Gerrit Jan Hemink, et al. (hereafter Hemink).
Regarding Claim 1, Hsia discloses a multi-level implementing method in a 3D flash memory (Disclosing a multi-level method for programming 3D flash memory: Hsia, ¶[0013]), the method comprising:
securing a threshold voltage distribution region (Distributing voltage thresholds within a bounded region: Hsia, ¶[0034])
by narrowing a distribution (Forming compact voltage threshold distributions: Hsia, ¶[0032]) of an erase threshold voltage (Specifically forming narrow erase distributions: Hsia, ¶[0030])
during an erase operation of the 3D flash memory (Disclosing the process of narrow erase voltage thresholds in the context of an erase operation: Hsia, Figure 4A); and
setting multi-level program threshold voltages in the secured threshold voltage distribution region (Setting the remaining voltage thresholds evenly in the available voltage distribution region: Hsia, ¶[0034]),
wherein the securing includes:
applying an initial erase voltage to a selected word line (Disclosing an initial erase pulse: Hsia, ¶[0043])
corresponding to a memory cell that is a target of the erase operation among a plurality of word lines included in the 3D flash memory (Applying the initial erase pulse to an array or portions of an array as the target of the erase operation: Hsia, ¶[0044]);
applying a read voltage to the selected word line (Disclosing ‘testing’ – reading – the erased memory cells: Hsia¶[0044]); and
applying an additional erase voltage to the selected word line (Applying additional erase pulses to the targeted memory cells: Hsia, ¶[0044]),
wherein the applying of the read voltage and the applying of the additional erase voltage are sequentially repeated until the distribution of the erase threshold voltage is narrowed to a level of a distribution of one of the multi-level program threshold voltages (Erasing memory cells to a tight, low sigma, distribution of erasure approximately equivalent to narrow program Vt distributions: Hsia, ¶[0030]).
Hsia fails to teach a 3D flash memory architecture wherein the 3D flash memory includes a substrate, a plurality of word lines extending in a horizontal direction, a plurality of interlayer insulating layers alternately stacked with the plurality of word lines in a vertical direction, and a plurality of vertical channel structures extending in the vertical direction through the plurality of word lines and the plurality of interlayer insulating layers, wherein the vertical direction is perpendicular to a top surface of the substrate, and the horizontal direction is parallel to the top surface of the substrate. Dong, however, discloses a 3D flash memory wherein:
wherein the 3D flash memory includes
a substrate (A substrate: Dong, ¶[0043]),
a plurality of word lines extending in a horizontal direction (Word lines extending horizontal to the substrate: Dong, ¶[0043]),
a plurality of interlayer insulating layers alternately stacked with the plurality of word lines in a vertical direction (Alternating insulating layers and conductive word lines: Dong, ¶[0043]; Dong does not expressly describe the alternating layers as insulating, but the insulating properties of the alternate layers are necessary for proper signal propagation), and
a plurality of vertical channel structures extending in the vertical direction through the plurality of word lines and the plurality of interlayer insulating layers (A plurality of vertical channel structures through the alternating layers: Dong, ¶[0043]),
wherein the vertical direction is perpendicular to a top surface of the substrate, and the horizontal direction is parallel to the top surface of the substrate (Disclosing the wordlines being horizontal, i.e. on plane with, the substrate. Vertical is definitionally normal to horizontal: Dong, ¶[0043]),
Dong teaches this 3D architecture avoids the inconvenience and lack of flexibility typically present in 3D NAND flash memory and allows erase operation be performed in groups of memory cells smaller than a block (Dong, ¶[0041]). Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of this application, to combine the reduced erase block size architecture of Dong with the narrowed erase voltage threshold methodology of Hsia, with a reasonable expectation of success. Both inventions were well known in the field of NAND Flash erase operation optimization and the combination of known inventions with predictable results is obvious and not patentable.
Neither Hsia nor Dong teach sequentially applying the erase and read operations, wherein the additional erase voltage has a value smaller than the initial erase voltage. Hemink, however, discloses an erase operation wherein:
wherein the applying of the read voltage and the applying of the additional erase voltage are sequentially repeated (Iteratively applying erase pulse and verification operations: Hemink, col.14:47-65)
wherein the additional erase voltage has a value smaller than the initial erase voltage (Decreasing the subsequent erase pulse: Hemink, col.14:56-57).
Hemink teaches reducing the size of the erase pulses allows for better control of the shift in threshold voltage, allowing more accurate control of the shift (Hemink, col.15:1-7). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to combine the accurate erase method of Hemink with the narrowed erase voltage threshold methodology of Hsia, with a reasonable expectation of success. Both inventions were well known in the field of NAND flash erase operation optimization and the combination of known inventions with predictable results is obvious and not patentable.
Regarding Amended Claim 3, Hemink discloses the method of claim 1, wherein
in each repetition of the applying of the read voltage and the applying of the additional erase voltage, the distribution of the erase threshold voltage is narrower than a distribution of the erase threshold voltage resulting from an immediately preceding erase voltage application (Reducing the voltage of each erase pulse allowing more accurate control of the erase operation, resulting in erase threshold voltage distributions more accurately positioned near the Everify level: Hemink, col.15:1-7).
Regarding Claim 4, Hemink discloses an erase operation as in Claim 3, wherein
the additional erase voltage applied in a subsequent repetition has a smaller value than the additional erase voltage applied in an immediately preceding repetition (Iteratively reducing the voltage of each erase pulse: Hemink, col.14:66-15:7).
Regarding Amended Claim 5, Hemink discloses an erase operation as in Claim 2, wherein
each application of the additional erase voltage narrows the distribution of the erase threshold voltage to one-half of a distribution level of the erase threshold voltage resulting from an immediately preceding erase voltage application (Reducing the voltage of each erase pulse allowing more accurate control of the erase operation, resulting in erase threshold voltage distributions more accurately positioned near the Everify level: Hemink, col.15:1-7).
Response to Arguments
Applicant’s arguments have been carefully considered but are deemed unpersuasive.
Applicant argues prior art Hsia fails to disclose applying the erase/read sequence repeatedly until the distribution of the erase threshold voltage is narrowed to a level of a distribution of one of the multi-level program threshold voltages (Applicant’s Arguments/Remarks, p.7¶2). Instead, Applicant contends, Hsia ends its erase phases based on whether cells have reached predetermined intermediate or threshold-voltage values. Hsia, however, states in ¶30, “In addition, the cells need to be erased to a well controlled narrow erase distribution (tight bit compacting) to insure subsequent program operations also will produce narrow program Vt distributions.” This clearly equates the target erase threshold voltage distribution to the similarly described program Vt distributions.
As such, it may be understood the erase process in Hsia has two goals: A. Reaching the appropriate erase voltage threshold and B. creating or maintaining a narrow threshold voltage distribution. This is similar to the present application, which states, “As such, step S420 and step S430 may be sequentially repeated until the final distribution of erase threshold voltages is narrowed to the level of a distribution 320 of program threshold voltages.” (Specification, ¶[54]). Although not stated, it may be understood the erase process includes the separate requirement of reaching the intended erase voltage threshold.
Applicant also argues amended claim 5 should be allowed because it claims, as amended, “each application of the additional erase voltage narrows the distribution of the erase threshold voltage to one-half of a distribution level of the erase threshold voltage resulting from an immediately preceding erase voltage application,” and the halving of the voltage distribution is not taught in the prior art (Applicant’s Arguments/Remarks: p.8¶4).
The amount by which an additional erase pulse narrows the remaining erase distribution is a result-effective variable. Hemink teaches iteratively reducing the erase pulse voltage allows for more accurate control of the erase operation, resulting in a narrow erase threshold voltage distribution more accurately positioned near the target voltage threshold (Hemink, col.15:1-7). A person of ordinary skill the art, before the effective filing date of this application, would have recognized that further reducing the additional erase step size results in a narrower threshold voltage distribution and increasing the step size results in a wider threshold voltage distribution. Discovering a step size that cuts the remaining width approximately in half on each iteration is no more than routine optimization of that known variable, undertaken to reach the compact erase distribution Hsia already identifies as the goal for multi-level programming. See MPEP § 2144.05(II) (Optimization of a result-effective variable is obvious unless the claimed value produces a new and unexpected result). Applicant has not shown that a one-half reduction per additional erase pulse yields a result different in kind from the progressive compaction already taught, or that the art teaches away from selecting this degree of narrowing. Claim 5 is therefore obvious.
Applicant’s remaining arguments filed with respect to the claims have been fully considered but are thought to be fully addressed by the modified and new grounds of rejections above. Applicant’s response is considered to be a bona fide attempt at a response and is being accepted as a complete response.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 7,057,936 B2 to Toshitake Yaegashi, et al.: Teaching reducing the relative voltage of iterative erase pulses to narrow the voltage distribution of memory cells.
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/CHRISTOPHER LANE REECE/Examiner, Art Unit 2824
/JEROME LEBOEUF/Primary Examiner, Art Unit 2824 - 08/31/2026
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