DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species A (claims 1-8 and 16) in the reply filed on 08 July 2026 is acknowledged.
Claims 9-15 and 17 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Species B, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 08 July 2026.
The requirement is still deemed proper and is therefore made FINAL.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-2, 4, 7 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Nakayama (WO 2020/202789 A1; see NPL for English translation) in view of Law (US 6,711,904 B1).
Regarding claim 1, Nakayama teaches a semiconductor apparatus (200; Figs. 12-13; note: this is a variant of Figs. 1-3 and other embodiments in Figs. 7-11) comprising:
a package substrate (10; see Fig. 3) having a recess portion (11) on a first surface (top surfaces of 10, which includes 111a & 112a);
a sensor chip (40) disposed inside the recess portion and having a pixel region (P; see Fig. 13) in which photoelectric conversion sections (213) are arranged;
a transparent cover plate (60, which is comprised of sealing glass 61; see Fig. 3) disposed on the first surface and covering an opening portion (111) of the recess portion.
Nakayama further teaches an element region (R1; see Figs. 12 & 13) of the sensor chip where the photoelectric conversion sections are disposed (see Figs. 12 & 13) and a peripheral region (R2) where the photoelectric conversions are not disposed and further teaches the sensor chip to be made of a semiconducting material such as silicon (¶ [0018]). However, Nakayama does not teach: a thermoelectric element module disposed between the sensor chip and the cover plate, wherein the thermoelectric element module includes a first electrode formed in a region within a surface of the sensor chip facing the cover plate, the region being on an edge side of the sensor chip with respect to the pixel region, a second electrode formed in a region within a surface of the cover plate facing the sensor chip, the region facing the region on the edge side, and at least a pair of thermoelectric elements disposed between the first and second electrodes and configured to be electrically connected to the first and second electrodes so as to absorb heat from the sensor chip and dissipate the heat to the cover plate.
Law, in the same field of invention, teaches a semiconductor apparatus comprising:
a thermoelectric element module (208&210&212&214&216&206&204; Figs. 2-3) disposed between the sensor chip (202; see Col. 5, Ln. 21: 202 is a semiconductor die) and the cover plate (218), wherein the thermoelectric element module includes
a first electrode (206&204) formed in a region (regions of 202/302 where 206 is formed; see also Fig. 3) within a surface (top surface of 202/302) of the sensor chip facing the cover plate, the region being on an edge side (Nakayama in view of Law teaches this edge side to be the top side of peripheral region R2 in Nakayama Fig. 12; see discourse below) of the sensor chip with respect to the pixel region,
a second electrode (212 & 214 & 216; Fig. 2) formed in a region (regions of 218/318 where 212 & 214 & 216 are formed; see Fig. 3) within a surface (bottom surface of 218) of the cover plate (218) facing the sensor chip, the region facing the region on the edge side (Nakayama in view of Law teaches this; see discourse below), and
at least a pair of thermoelectric elements (208 & 210) disposed between the first and second electrodes (see Fig. 2) and configured to be electrically connected to the first and second electrodes so as to absorb heat from the sensor chip and dissipate the heat to the cover plate (see Col. 5, Ln 20 through Col. 6., Ln. 7).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Law into the device of Nakayama to add at least one thermoelectric element module comprised of a first electrode, and second electrode, and a pair of thermoelectric elements, wherein the thermoelectric module disposed in between the sensor chip and the cover plate, wherein the first electrode is connected on a top side of the sensor chip, wherein the second electrode is connected on a bottom side of the cover plate, and wherein these thermoelectric elements are added at the peripheral region of the sensor chip. The ordinary artisan would have been motivated to modify Nakayama in the manner set forth above for at least the purpose of improving the heat dissipation, performance, and life expectancy of the semiconductor apparatus (Col. 1, Ln, 19 through Col. 2, Ln. 5), such that the light sensed by the sensor is not impeded by placing the first electrode of the thermoelectric module in the edge side (i.e., peripheral regions R2 of Nakayama) of the sensor chip (see MPEP 2144 (I): use of common knowledge in the art and scientific principles).
Regarding claim 2, the semiconductor apparatus according to claim 1, further comprising: a Peltier element (20; see Nakayama Fig. 3) disposed between the sensor chip and a bottom surface (112a) of the recess portion and configured to absorb heat from the sensor chip and dissipate the heat to the package substrate (¶ [0020] ).
Regarding claim 4, the semiconductor apparatus according to claim 1, further comprising: a sealing member (15; see Nakayama Fig. 2) that is disposed between the first surface and the cover plate so as to surround the opening portion of the recess portion and that hermetically seals an interior space of the recess portion (¶ [0015]: 15 is a seal ring; ¶ [0026]: package is hermetically sealed).
Regarding claim 7, the semiconductor apparatus according to claim 1, wherein the first electrode includes a pad (204; see Law Fig. 2) formed in the region on the edge side of the sensor chip (Nakayama in view of Law teaches this; see claim 1 rejection above) and connected to a wiring (pad 204 is part of feedback loop comprised of power supply 220, controller 224, and temperature performance monitor 222) inside the sensor chip (Figs. 2 and 5 shows the wiring being fed into the chip 202 / 502; see also Col. 7, Ln. 7 through Col. 8, Ln 6).
Regarding claim 16, Nakayama teaches an electronic device comprising:
a semiconductor apparatus 200; Figs. 12-13; note: this is a variant of Figs. 1-3 and other embodiments in Figs. 7-11) including
a package substrate (10; see Fig. 3) having a recess portion (11) on a first surface (top surfaces of 10, which includes 111a & 112a),
a sensor chip (40) disposed inside the recess portion and having a pixel region (P; see Fig. 13) in which photoelectric conversion sections (213) are arranged,
a transparent cover plate (60, which is comprised of sealing glass 61; see Fig. 3) disposed on the first surface and covering an opening portion (111) of the recess portion.
Nakayama further teaches an element region (R1) of the sensor chip where the photoelectric conversion sections are disposed (see Fig. 12) and a peripheral region (R2) where the photoelectric conversions are not disposed and further teaches the sensor chip to be made of a semiconducting material such as silicon (¶ [0018]). However, Nakayama does not teach: a thermoelectric element module disposed between the sensor chip and the cover plate, wherein the thermoelectric element module includes a first electrode formed in a region within a surface of the sensor chip facing the cover plate, the region being on an edge side of the sensor chip with respect to the pixel region, a second electrode formed in a region within a surface of the cover plate facing the sensor chip, the region facing the region on the edge side, and at least a pair of thermoelectric elements disposed between the first and second electrodes and configured to be electrically connected to the first and second electrodes so as to absorb heat from the sensor chip and dissipate the heat to the cover plate.
Law, in the same field of invention, teaches an electronic device comprising:
a thermoelectric element module (208&210&212&214&216&&204&206) disposed between the sensor chip (202; see Col. 5, Ln. 21: 202 is a semiconductor die) and the cover plate (218), wherein the thermoelectric element module includes
a first electrode (204&206) formed in a region (regions of 202/302 where 206 is formed; see Figs. 2-3) within a surface (top surface of 202/302) of the sensor chip facing the cover plate, the region being on an edge side (Nakayama in view of Law teaches this edge side to be the top side of peripheral region R2 in Nakayama Fig. 12; see discourse below) of the sensor chip with respect to the pixel region,
a second electrode (212 & 214 & 216) formed in a region (region of 218/318 where 212 & 214 & 216 are formed; see Fig. 3) within a surface (bottom surface of 218) of the cover plate (218) facing the sensor chip, the region facing the region on the edge side (Nakayama in view of Law teaches this; see discourse above), and
at least a pair of thermoelectric elements (208 & 210) disposed between the first and second electrodes (see Fig. 2) and configured to be electrically connected to the first and second electrodes so as to absorb heat from the sensor chip and dissipate the heat to the cover plate (see Col. 5, Ln 20 through Col. 6., Ln. 7).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Law into the device of Nakayama to add a thermoelectric element module comprised of a first electrode, and second electrode, and a pair of thermoelectric elements, wherein the thermoelectric module disposed in between the sensor chip and the cover plate, wherein the first electrode is connected to a top side of the sensor chip, wherein the second electrode is connected to a bottom side of the cover plate, and wherein these thermoelectric elements are added at the peripheral region of the sensor chip. The ordinary artisan would have been motivated to modify Nakayama in the manner set forth above for at least the purpose of improving the heat dissipation, performance, and life expectancy of the semiconductor apparatus (Col. 1, Ln, 19 through Col. 2, Ln. 5), such that the light sensed by the sensor is not impeded by placing the first electrode of the thermoelectric module in the edge side (i.e., peripheral region) of the sensor chip (see MPEP 2144 (I): use of common knowledge in the art and scientific principles).
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Nakayama (WO 2020/202789 A1) in view of Law (US 6,711,904 B1) as applied to claim 1 above, and further in view of Amano (US 2010/0243872 A1).
Regarding claim 3, Nakayama et al. teaches the semiconductor apparatus according to claim 1, but does not teach the device further comprising: a heat dissipation mechanism disposed on a surface of the package substrate opposite the first surface and configured to dissipate heat of the package substrate.
Amano, in the same field of invention, teaches a semiconductor apparatus comprising: a heat dissipation mechanism (6; see Fig. 2) disposed on a surface (bottom surface of 3) of the package substrate (3) opposite the first surface and configured to dissipate heat of the package substrate (see ¶ [0047] ).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Amano into the device of Nakayama et al. to add a heat dissipation element at the bottom surface of the package substrate. The ordinary artisan would have been motivated to modify Nakayama et al. in the manner set forth above for at least the purpose of improving the heat dissipation of the package and the performance of the device (¶ [0007]-[0010]) .
Claim 5-6 are rejected under 35 U.S.C. 103 as being unpatentable over Nakayama (WO 2020/202789 A1) in view of Law (US 6,711,904 B1) as applied to claim 1 above, and further in view of Kurioka (US 2010/0020469 A1).
Regarding claim 5, Nakayama et al. teach the semiconductor apparatus according to claim 4, and further teaches the sealing member to be made of Kovar (Nakayama ¶ [0021] of the English translation). However, Nakayama et al. do not teach: wherein a material for the sealing member includes a solder.
Kurioka, in the same field of invention, teaches wherein a material for the sealing member (26) includes either Kovar (¶ [0055]) or a solder (¶ [0209]).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to substitute the Kovar material of the sealing member with that of a solder for the same purpose of connecting the cover plate (25; Kurioka Fig. 1) with the substrate (28&41; Fig. 19 & ¶ [0209]).
Regarding claim 6, Nakayama et al. teach the semiconductor apparatus according to claim 4, and further teaches the sealing member to be made of Kovar (Nakayama ¶ [0021] of the English translation). However, Nakayama et al. do not teach: the semiconductor apparatus according to claim 4, wherein a material for the sealing member includes a resin.
Kurioka, in the same field of invention, teaches wherein a material for the sealing member includes either Kovar (¶ [0055]) or a resin (¶ [0209]).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to substitute the Kovar material of the sealing member with that of a resin for the same purpose of connecting the cover plate (25; Kurioka Fig. 1) with the substrate (27&41; Fig. 19 & ¶ [0209]).
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Nakayama (WO 2020/202789 A1) in view of Law (US 6,711,904 B1) as applied to claim 1 above, and further in view of Maliik (US 2005/0127489 A1).
Regarding claim 8, Nakayama et al. teaches the semiconductor apparatus according to claim 1, but does not teach the device to comprise: an interior wiring disposed inside a wall portion of the recess portion of the package substrate and having one end connected to a first terminal exposed to a surface of the package substrate opposite the first surface and another end connected to a second terminal exposed to the first surface, wherein the second terminal and the second electrode are configured to be electrically connected to each other.
Maliik, in the same field of invention, teaches a device comprising: an interior wiring (274; see Fig. 6) disposed inside a wall portion (vertical sidewalls of 262) of the recess portion (268) of the package substrate (262) and having one end (bottom end of 274) connected to a first terminal (272) exposed to a surface (bottom surface of 262) of the package substrate opposite the first surface (top surfaces of 262) and another end (top end of 274) connected to a second terminal (232) exposed to the first surface (232 is above the top surfaces of 262), wherein the second terminal and the second electrode are configured to be electrically connected to each other (see ¶ [0040] ).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Maliik into the device of Nakayama to add an interior wiring to the semiconductor apparatus in the manner described above. The ordinary artisan would have been motivated to modify Nakayama et al. in the manner set forth above for at least the purpose of delivering external signals to the sensor chip and/or delivering output signals of the sensor chip to an external device (see Maliik ¶ [0040]: 274 is part of a signal trace ) for the further purpose of shortening the length of the path of the signal (¶ [0040]), improving the latency of the device and device density, and reducing cost (¶ [0004]- [0006] ).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DOUGLAS YAP whose telephone number is (703)756-1946. The examiner can normally be reached Monday - Friday 8:00 AM - 5:00 PM ET.
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/DOUGLAS YAP/Assistant Examiner, Art Unit 2899
/JOHN M PARKER/Primary Examiner, Art Unit 2899
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