Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
This Office Action is in response to the application filed 04/19/2024. Claims 1-20 are presently pending and are presented for examination. Claims 21-30 are canceled.
Information Disclosure Statement
The Information Disclosure Statement filed on 01/15/2025 has been considered. An initialed copy of the Form 1449 is enclosed herewith.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-11 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Iwase et. al. (J.P. Publication No. 2007/227953 A)-IDS in view of Thaulad et. al. (U.S. Publication No. 2020/0144097)-IDS in further view of Yamamoto et. al. (U.S. Publication No. 2009/0133551).
Regarding claim 1
Iwase discloses “A calibration wafer for use in a semiconductor processing tool, the calibration wafer comprising:”… “two or more cutouts arranged along the outer edge;” (See Iwase [0042] disclosing ID marking printed with respect to notches on a calibration wafer, thus implying a plurality of notches.).
Iwase discloses “and a plurality of fiducial markers,” (See Iwase [0067] and Fig. 5, Chars. 24a, 24b and 24c, disclosing ID marking printed on the peripheral portion of a wafer, adjacent to the notch in the wafer (23).).
Iwase discloses “and one or more fiducial markers are adjacent to each cutout.” (See Iwase [0067] and Fig. 5, Chars. 24a, 24b and 24c, disclosing ID marking printed on the peripheral portion of a wafer, adjacent to the notch in the wafer (23).).
Iwase discloses all the elements of claim 1 except “a nominally circular disk shape having an outer edge with a nominal diameter selected from the group consisting of: 200mm : ± 1 mm, 300mm : ± 1 mm, and 450mm : ± 1 mm;”, & “wherein: each cutout is at least partially defined by one or more edges, each cutout extends radially inwards at least 2mm from a reference circle defined by the outer edge,”
Thaulad discloses “a nominally circular disk shape having an outer edge with a nominal diameter selected from the group consisting of: 200mm : ± 1 mm, 300mm : ± 1 mm, and 450mm : ± 1 mm;” (See Thaulad [0050] disclosing a calibration wafer for use in a semiconductor processing tool may be a circular disk that has a known diameter such as 300 mm.).
Iwase and Thaulad are analogous art, because they are in the same field of endeavor, robotics. It would have been obvious for one of ordinary skill in the art, before the effective filing date of the claimed invention to have modified Iwase to incorporate the teachings of Thaulad to include a calibration wafer with the claimed shape and diameter. Doing so provides a known structure in the art for designing a wafer in a semiconductor processing system, incorporated with a reasonable expectation of success as doing so merely incorporates an obvious design choice, see Seid, 161 F.2d 229, 73 USPQ 431, & Japikse, 181 F.2d 1019, 86 USPQ 70.
Yamamoto discloses “wherein: each cutout is at least partially defined by one or more edges, each cutout extends radially inwards at least 2mm from a reference circle defined by the outer edge,” (See Yamamoto [0069] disclosing a wafer with a cutout approximately 3 mm in depth.).
Iwase and Yamamoto are analogous art, because they are in the same field of endeavor, robotics. It would have been obvious for one of ordinary skill in the art, before the effective filing date of the claimed invention to have modified Iwase to incorporate the teachings of Yamamoto to include a cutout on a wafer with the claimed geometry. Doing so provides a known structure in the art for designing a wafer in a semiconductor processing system, incorporated with a reasonable expectation of success as doing so merely incorporates an obvious design choice, see Seid, 161 F.2d 229, 73 USPQ 431, & Japikse, 181 F.2d 1019, 86 USPQ 70.
Regarding claim 2
Iwase discloses “The calibration wafer of claim 1, wherein for each cutout, at least one fiducial marker extends around at least one edge of the one or more edges of the cutout.” (See Iwase [0067] and Fig. 5, Chars. 24a, 24b and 24c, disclosing ID marking printed on the peripheral portion of a wafer, adjacent to the notch in the wafer (23) extending around the edges of the notch.).
Regarding claim 3
Iwase discloses “The calibration wafer of claim 2, wherein: each cutout has a shape, and at least one fiducial marker has a substantially similar shape to the shape of the cutout.” (See Iwase [0080] disclosing a reference position is a reference object or a reference symbol indicating the crystal orientation of a wafer. The reference object or reference symbol including a wafer orientation flat, a notch or a fine marking.).
Regarding claim 4
Iwase discloses “The calibration wafer of claim 2, wherein for each cutout, at least one fiducial marker is adjacent to the least one edge of the cutout.” (See Iwase [0067] and Fig. 5, Chars. 24a, 24b and 24c, disclosing ID marking printed on the peripheral portion of a wafer, adjacent to the notch in the wafer (23).).
Regarding claim 5
Iwase discloses “The calibration wafer of claim 1, wherein for each cutout, at least one fiducial marker has a section that extends along at least a part of at least one edge of the cutout and is offset from the at least one edge by a substantially constant offset distance.” (See Iwase Fig. 1, Chars. 13, and 14a-14d & [0041] disclosing ID marking printed adjacent to a notch, the individual ID marks continuously imprinted at a certain distance, for example, every 100 μm.).
Regarding claim 6
Iwase discloses “The calibration wafer of claim 1, wherein for each cutout, at least one fiducial marker is positioned within a distance of about 5mm or less from one edge of the corresponding cutout.” (See Iwase Fig. 1, Chars. 13, and 14a-14d & [0041] disclosing ID marking printed adjacent to a notch, the individual ID marks continuously imprinted at a certain distance, for example, every 100 μm.).
Regarding claim 7
Iwase discloses “The calibration wafer of claim 1, wherein for each cutout, at least one fiducial marker has a width between about 3mm and about 0.01mm.” (See Iwase [0030] disclosing the ID markings printed may generally range as about 100 to 200 μm (.1- .2 mm) in width.).
Regarding claim 8
Iwase discloses “The calibration wafer of claim 1, wherein for each cutout, at least one fiducial marker has a shape of a C-shape, an L-shape, a semi-circular shape, a partially obround shape, a linear shape, a plurality of lines, a non-linear shape, or one or more linear sections and one or more non-linear sections.” (See Iwase Fig. 3, Chars. 23 and 24a-24c, depicting three markers adjoining a notch, each forming a plurality of lines.).
Regarding claim 9
Iwase discloses “The calibration wafer of claim 1, wherein: each cutout includes at least four fiducial markers that form a pattern, and the pattern is a plurality of circles, a plurality of triangles, a plurality of squares, a plurality of rectangles, a plurality of diamonds, a plurality of squares with at least two squares in contact with each other, a checkerboard, or a combination thereof.” (See Iwase Fig. 1, Chars. 13 and 14a-14d, depicting four markers adjoining a notch, each forming a rectangular shape.).
Regarding claim 10
Iwase discloses “The calibration wafer of claim 1, wherein for each cutout, at least one fiducial marker has a linear shape and is oriented along an axis that substantially intersects with a center of the calibration wafer.” (See Iwase [0030] disclosing the ID marks may be arranged in a vertical or horizontal matrix, which would form a line (linear shape) on an axis that intersects with the center of the wafer.).
Regarding claim 11
Iwase discloses “The calibration wafer of claim 1, wherein: when viewed along an axis parallel to a center axis of the calibration wafer, each cutout has a shape, and the shape is a square, a square with rounded corners, a rectangle, a rectangle with rounded corners, a V-shape, a circle, a semi-circle, a triangle, a triangle with rounded corners, an obround shape, an ellipse, a hexagon, a pentagon, an octagon, a shape with linear and non-linear sections, or a shape with a plurality of linear sections.” (See Iwase Fig. 1, Char. 13, depicting the notch as a semi-circle when viewed from above.).
Regarding claim 16
Iwase discloses “The calibration wafer of claim 1, wherein each cutout is a through-hole.” (See Iwase Fig. 1, Char. 13, depicting the notch as a through-hole semi-circle when viewed from above.).
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Iwase et. al. (J.P. Publication No. 2007/227953 A)-IDS in view of Thaulad et. al. (U.S. Publication No. 2020/0144097)-IDS in further view of Yamamoto et. al. (U.S. Publication No. 2009/0133551) in even further view of Yoshizumi et. al. (U.S. Publication No. 2020/0255979).
Regarding claim 12
Iwase modified in view of Thaulad and Yamamoto discloses “The calibration wafer of claim 1” and further discloses all the elements of claim 12 except “wherein: when viewed along an axis parallel to a center axis of the calibration wafer, each cutout has a shape, and the shape has a width less than or equal to about 10mm and a length less than or equal to about 10mm.”
Yoshizumi discloses “wherein: when viewed along an axis parallel to a center axis of the calibration wafer, each cutout has a shape, and the shape has a width less than or equal to about 10mm and a length less than or equal to about 10mm.” (See Yoshizumi [0037] disclosing a notch in a crystal substrate cut off a portion not smaller than 0.5 mm and not greater than 1.5 mm from the outer edge toward the center, thus with a width and length less than 10mm.).
Iwase and Yoshizumi are analogous art, because they are in the same field of endeavor, robotics. It would have been obvious for one of ordinary skill in the art, before the effective filing date of the claimed invention to have further modified Iwase to incorporate the teachings of Yoshizumi to include a cutout on a wafer with the claimed geometry. Doing so provides a known structure in the art for designing a wafer in a semiconductor processing system, incorporated with a reasonable expectation of success as doing so merely incorporates an obvious design choice, see Seid, 161 F.2d 229, 73 USPQ 431, & Japikse, 181 F.2d 1019, 86 USPQ 70.
Claims 13-15 are rejected under 35 U.S.C. 103 as being unpatentable over Iwase et. al. (J.P. Publication No. 2007/227953 A)-IDS in view of Thaulad et. al. (U.S. Publication No. 2020/0144097)-IDS in further view of Yamamoto et. al. (U.S. Publication No. 2009/0133551) in even further view of Hung et. al. (U.S. Publication No. 2003/0135302)-IDS.
Regarding claim 13
Iwase modified in view of Thaulad and Yamamoto discloses “The calibration wafer of claim 1” and further discloses all the elements of claim 13 except “further comprising three or more cutouts arranged along the outer edge.”
Hung discloses “further comprising three or more cutouts arranged along the outer edge.” (See Hung [0050] and Fig. 5, Char. 70 disclosing a calibration tool includes three cutouts or notches formed in an outer edge.).
Iwase and Hung are analogous art, because they are in the same field of endeavor, robotics. It would have been obvious for one of ordinary skill in the art, before the effective filing date of the claimed invention to have further modified Iwase to incorporate the teachings of Hung to include three or more cutouts on a wafer with the claimed positioning. Doing so provides a known structure in the art for designing a wafer in a semiconductor processing system, incorporated with a reasonable expectation of success as doing so merely incorporates an obvious design choice, see Seid, 161 F.2d 229, 73 USPQ 431, & Japikse, 181 F.2d 1019, 86 USPQ 70.
Regarding claim 14
Iwase modified in view of Thaulad and Yamamoto discloses “The calibration wafer of claim 1” and further discloses all the elements of claim 14 except “wherein the cutouts are arranged in a circular array about a center point of the calibration wafer.”
Hung discloses “wherein the cutouts are arranged in a circular array about a center point of the calibration wafer.” (See Hung [0050] and Fig. 5, Char. 70 disclosing a calibration tool includes three cutouts or notches formed in an outer edge arranged in a circular array about the center of the wafer.).
The rationale for forming the combination is similar to the rationale provided in the rejection of claim 13.
Regarding claim 15
Iwase modified in view of Thaulad, Yamamoto, and Hung discloses “The calibration wafer of claim 14,” and further discloses all the elements of claim 15 except “wherein the cutouts are spaced substantially equally from each other about the center point.”
Hung discloses “wherein the cutouts are spaced substantially equally from each other about the center point.” (See Hung [0050] and Fig. 5, Chars. 69, 70, and 72 disclosing the distance between the most outer edge of the tool and the inner edge defined by the notch is equal to the thickness of the clamp wall, thus the notches must be equally spaced.).
The rationale for forming the combination is similar to the rationale provided in the rejection of claim 13.
Claims 17-18 are rejected under 35 U.S.C. 103 as being unpatentable over Iwase et. al. (J.P. Publication No. 2007/227953 A)-IDS in view of Thaulad et. al. (U.S. Publication No. 2020/0144097)-IDS in further view of Yamamoto et. al. (U.S. Publication No. 2009/0133551) in even further view of Nakayama et. al. (U.S. Publication No. 2005/0145879)-IDS.
Regarding claim 17
Iwase modified in view of Thaulad and Yamamoto discloses “The calibration wafer of claim 1, further comprising: a top surface;” (See Iwase [0026] and Fig. 1, Char. 12, depicting a wafer with a bevel portion, thus a top surface and bottom surface.).
Iwase further discloses “and a bottom surface opposite the top surface and at least partially defining a nominal thickness,” (See Iwase [0026] and Fig. 1, Char. 12, depicting a wafer with a bevel portion, thus a top surface and bottom surface.).
Iwase discloses all the elements of the claim 17 except “wherein: the top surface has a different surface roughness than the bottom surface.”.
Nakayama discloses “wherein: the top surface has a different surface roughness than the bottom surface.” (See Nakayama Abstract and claim 1 disclosing a top surface roughness of 0.1 nm≦RMS≦5 nm or more favorably 0.1 nm≦RMS≦0.5 nm and the bottom surface has roughness RMS of 0.1 nm≦RMS≦5000 nm or more favorably 0.1 nm≦RMS≦2 nm.).
Iwase and Nakayama are analogous art, because they are in the same field of endeavor, robotics. It would have been obvious for one of ordinary skill in the art, before the effective filing date of the claimed invention to have further modified Iwase to incorporate the teachings of Nakayama to include different surface roughness for a top and bottom surface of a wafer. Doing so provides a known structure in the art for designing a wafer in a semiconductor processing system, incorporated with a reasonable expectation of success as doing so merely incorporates an obvious design choice, see Seid, 161 F.2d 229, 73 USPQ 431, & Japikse, 181 F.2d 1019, 86 USPQ 70, which advantageously provides a known solution for wafers in the art see Nakayama [0025].
Regarding claim 18
Iwase modified in view of Thaulad, Yamamoto, and Nakayama discloses “The calibration wafer of claim 17” and further discloses all the elements of claim 18 except “wherein the top surface is a lapped or polished surface.”.
Nakayama discloses “wherein the top surface is a lapped or polished surface.” (See Nakayama Abstract disclosing a top surface as polished.).
The rationale for forming the combination is similar to the rationale provided in the rejection of claim 17.
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Iwase et. al. (J.P. Publication No. 2007/227953 A)-IDS in view of Thaulad et. al. (U.S. Publication No. 2020/0144097)-IDS in further view of Yamamoto et. al. (U.S. Publication No. 2009/0133551) in even further view of Cahill et. al. (U.S. Publication No. 2004/0031779).
Regarding claim 19
Iwase modified in view of Thaulad and Yamamoto discloses “The calibration wafer of claim 1,” and further discloses all the elements of claim 19 except “further comprising a nominal thickness of between about 0.5mm and about 1.5mm.”.
Cahill further discloses “further comprising a nominal thickness of between about 0.5mm and about 1.5mm.” (See Cahill [0078] disclosing a wafer with thickness ranges of about 300 μm to 775 μm.).
Iwase and Cahill are analogous art, because they are in the same field of endeavor, robotics. It would have been obvious for one of ordinary skill in the art, before the effective filing date of the claimed invention to have further modified Iwase to incorporate the teachings of Cahill to include the claimed wafer thickness. Doing so provides a known structure in the art for designing a wafer in a semiconductor processing system, incorporated with a reasonable expectation of success as doing so merely incorporates an obvious design choice, see Seid, 161 F.2d 229, 73 USPQ 431, & Japikse, 181 F.2d 1019, 86 USPQ 70.
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Iwase et. al. (J.P. Publication No. 2007/227953 A)-IDS in view of Thaulad et. al. (U.S. Publication No. 2020/0144097)-IDS in further view of Yamamoto et. al. (U.S. Publication No. 2009/0133551) in even further view of Sadeghi et. al. (W.O. Publication No. 2021/022291 A1)-IDS.
Regarding claim 20
Iwase modified in view of Thaulad and Yamamoto discloses “The calibration wafer of claim 1,” and further discloses all the elements of claim 20 except “further comprising: one or more through-holes in an interior region of the calibration wafer; and a second plurality of fiducial markers, wherein: each through-hole is at least partially defined by one or more edges, and one or more fiducial markers of the second plurality of fiducial markers are adjacent to each through-hole.”.
Sadeghi further discloses “further comprising: one or more through-holes in an interior region of the calibration wafer; and a second plurality of fiducial markers, wherein: each through-hole is at least partially defined by one or more edges, and one or more fiducial markers of the second plurality of fiducial markers are adjacent to each through-hole.” (See Sadeghi [0082] disclosing fiducials may be used in an inner circular edge of an edge ring encircling a semiconductor wafer. The relative sizes of the radial gaps between the outer edge of the semiconductor wafer and the inner edge of the edge ring in each image may be determined and used to generate an estimate of the degree to which the center of the semiconductor wafer is offset from the center of the edge ring.).
Iwase and Sadeghi are analogous art, because they are in the same field of endeavor, robotics. It would have been obvious for one of ordinary skill in the art, before the effective filing date of the claimed invention to have further modified Iwase to incorporate the teachings of Sadeghi to include the claimed through-hole cutouts with adjoining markers. Doing so provides a known structure in the art for designing a wafer in a semiconductor processing system, incorporated with a reasonable expectation of success as doing so merely incorporates an obvious design choice, see Seid, 161 F.2d 229, 73 USPQ 431, & Japikse, 181 F.2d 1019, 86 USPQ 70.
Conclusion
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/JERROD IRVIN DAVIS/Examiner, Art Unit 3656
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