DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 26, 27 and 29 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 26 and 27 recite the limitation "the compound semiconductor material" in line 1 of each claim; claim 29 recites the limitation “the first semiconductor layer” in line 4. There is insufficient antecedent basis for these limitations in the claims.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim 1 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Beam, III et al (US Patent Application Publication 2017/0294529).
Regarding claim 1, Beam, III et al disclose a method of fabricating a heterostructure, the method comprising:
growing epitaxially, in a growth chamber, a first semiconductor layer 16 of the heterostructure, the first semiconductor layer comprising a III-nitride semiconductor material, the first semiconductor layer being supported by a substrate 14 [see Fig. 2; see also paragraph 0023, wherein the first semiconductor layer is comprised of epitaxial AlN]; and
after growing the first semiconductor layer, growing epitaxially, in the growth chamber, a second semiconductor layer 38 of the heterostructure such that the second semiconductor layer is supported by the first semiconductor layer, the second semiconductor layer comprising a quaternary or higher order III-nitride alloy [see Fig. 2; see also paragraph 0024, wherein the quaternary or higher order III-nitride alloy is ScAlGaN],
wherein the quaternary or higher order III-nitride alloy comprises a group IIIB element [see paragraph 0024].
Claims 1, 4 and 8 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Leone et al (US Patent Application Publication 2021/0066070).
Regarding claim 1, Leone et al disclose a method of fabricating a heterostructure, the method comprising:
growing epitaxially, in a growth chamber, a first semiconductor layer 23 of the heterostructure, the first semiconductor layer comprising a III-nitride semiconductor material, the first semiconductor layer being supported by a substrate 20 [see Fig. 1; see also paragraph 0070, wherein the first semiconductor layer is comprised of epitaxial AlN]; and
after growing the first semiconductor layer, growing epitaxially, in the growth chamber, a second semiconductor layer 24 of the heterostructure such that the second semiconductor layer is supported by the first semiconductor layer, the second semiconductor layer comprising a quaternary or higher order III-nitride alloy [see Fig. 1; see also paragraph 0070, wherein the quaternary or higher order III-nitride alloy is AlScN],
wherein the quaternary or higher order III-nitride alloy comprises a group IIIB element [see paragraph 0070].
Regarding claim 4, Leone et al disclose the method of claim 1, furthermore wherein growing the second semiconductor layer is implemented without removal of the substrate from the growth chamber after growth of the first semiconductor layer [see paragraphs 0066-0070, 0079 and 0098].
Regarding claim 8, Leone et al disclose the method of claim 1, furthermore wherein the group IIIB element is a lanthanide element [see paragraphs 0028 and 0059].
Claims 1, 5-7, 14, 16-23, 28 and 29 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hardy et al (US Patent Application Publication 2018/0130883).
Regarding claim 1, Hardy et al disclose a method of fabricating a heterostructure, the method comprising:
growing epitaxially, in a growth chamber, a first semiconductor layer 202 of the heterostructure, the first semiconductor layer comprising a III-nitride semiconductor material, the first semiconductor layer being supported by a substrate 201 [see Fig. 2; see also paragraph 0034]; and
after growing the first semiconductor layer, growing epitaxially, in the growth chamber, a second semiconductor layer 203 of the heterostructure such that the second semiconductor layer is supported by the first semiconductor layer, the second semiconductor layer comprising a quaternary or higher order III-nitride alloy [see Fig. 2; see also paragraph 0035, wherein the quaternary or higher order III-nitride alloy is ScAlN],
wherein the quaternary or higher order III-nitride alloy comprises a group IIIB element [see paragraph 0035].
Regarding claim 5, Hardy et al disclose the method of claim 1, furthermore wherein growing epitaxially the second semiconductor layer comprises adjusting a IIIB element/metal flux ratio during epitaxial growth of the second semiconductor layer [see paragraphs 0033-0037].
Regarding claim 6, Hardy et al disclose the method of claim 5, furthermore wherein the IIIB element/metal ratio is a scandium/aluminum flux ratio [see paragraph 0033-0037].
Regarding claim 7, Hardy et al disclose the method of claim 1, furthermore wherein growing epitaxially the second semiconductor layer is implemented with a flux ratio such that a composition of the group IIIB element falls in a range from about 0.10 to about 0.50 [see paragraphs 0033-0037, wherein the Sc and Al flux ratio falls in the range of about 0.16-0.20, which falls within the claimed range].
Regarding claim 14, Hardy et al disclose a device comprising:
a substrate 201; and
a semiconductor heterostructure supported by the substrate, the semiconductor heterostructure comprising:
a first semiconductor layer 202 supported by the substrate and comprising a III-nitride semiconductor material [see Fig. 2; see also paragraph 0034];
a second semiconductor layer 203 supported by the first semiconductor layer and comprising a quaternary or higher order III-nitride alloy, the quaternary or higher order III-nitride alloy comprising a group IIIB element [see Fig. 2; see also paragraph 0035, wherein the quaternary or higher order III-nitride alloy is ScAlN];
wherein the second semiconductor layer has a terraced surface distal to the first semiconductor layer [see Fig. 3C].
Regarding claim 16, Hardy et al disclose the device of claim 14, furthermore wherein a composition of the group IIIB element falls in a range from about 0.10 to about 0.50 [see paragraphs 0033-0037, wherein the Sc and Al flux ratio falls in the range of about 0.16-0.20, which falls within the claimed range].
Regarding claim 17, Hardy et al disclose the device of claim 14, furthermore wherein the second semiconductor layer is in contact with the first semiconductor layer [see Fig. 2].
Regarding claim 18, Hardy et al disclose the device of claim 14, furthermore comprising a third semiconductor layer disposed between the first and second semiconductor layers, wherein the third semiconductor layer comprises a further III-nitride semiconductor material differing from the III-nitride semiconductor material of the first semiconductor layer [see paragraphs 0033 and 0034].
Regarding claims 19 and 20, Hardy et al disclose the device of claim 14, furthermore wherein the first and second semiconductor layers are lattice matched or lattice mismatched [see paragraph 0031, wherein the layers are disclosed to be lattice matched or closely matched, which is lattice mismatched].
Regarding claim 21, Hardy et al disclose the device of claim 14, furthermore wherein the second semiconductor layer is configured as a dielectric layer [see paragraph 0035, wherein the second semiconductor layer is disclosed as an etch stop layer; one of ordinary skill in the art would recognize that etch stop layers are typical dielectric in nature in order to provide electrical isolation while also serving as a process stop layer, i.e. during etching].
Regarding claim 22, Hardy et al disclose a device comprising:
a substrate 201; and
a semiconductor heterostructure supported by the substrate, the semiconductor heterostructure comprising:
a first semiconductor layer 202 supported by the substrate and comprising a III-nitride semiconductor material [see Fig. 2; see also paragraph 0034];
a second semiconductor layer 203 supported by the first semiconductor layer and comprising a quaternary or higher order III-nitride alloy, the quaternary or higher order III-nitride alloy comprising a group IIIB element [see Fig. 2; see also paragraph 0035, wherein the quaternary or higher order III-nitride alloy is ScAlN];
wherein a composition of the group IIIB element falls in a range from about 0.10 to about 0.50 [see paragraphs 0033-0037, wherein the Sc and Al flux ratio falls in the range of about 0.16-0.20, which falls within the claimed range].
Regarding claim 23, Hardy et al disclose a transistor device comprising:
a substrate 201; and
a semiconductor heterostructure supported by the substrate, the semiconductor heterostructure comprising:
a buffer layer 202 supported by the substrate and comprising a III-nitride semiconductor material [see Fig. 2; see also paragraph 0034];
a barrier layer 203 supported by the buffer layer and comprising a quaternary or higher order III-nitride alloy, the quaternary or higher order III-nitride alloy comprising a group IIIB element [see Fig. 2; see also paragraph 0035, wherein the quaternary or higher order III-nitride alloy is ScAlN];
wherein the barrier layer has a terraced surface distal to the first semiconductor layer [see Fig. 3C].
Regarding claims 28, Hardy et al disclose the transistor device of claim 23, furthermore wherein the III-nitride semiconductor material and the quaternary or higher order III-nitride alloy are lattice mismatched [see paragraph 0031, wherein the layers are disclosed to be lattice matched or closely matched, which is lattice mismatched].
Regarding claim 29, Hardy et al disclose the transistor device of claim 23, furthermore comprising a further semiconductor layer disposed between the buffer and barrier layers, wherein the further semiconductor layer comprises a further III-nitride semiconductor material differing from the III-nitride semiconductor material of the first semiconductor layer [see paragraphs 0033 and 0034].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2, 3, 9 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Beam, III et al (US Patent Application Publication 2017/0294529) in view of Cuomo et al (US Patent Application Publication 2002/0078881).
Regarding claims 2 and 3, Beam, III et al disclose the method of claim 1. Beam, III et al do not disclose wherein growing epitaxially the second semiconductor layer is implemented in a metal-rich environment. One such as Cuomo et al disclose growing epitaxially a similar semiconductor layer in a gallium-rich or indium-rich environment [see Figs. 1 and 2; see also paragraphs 0081-0084 and 0096]. It would have been obvious to one of ordinary skill in the art at the time of invention to grow epitaxially the second semiconductor layer in a metal-rich environment, in order to promote columnar growth of group III nitrides.
Regarding claims 9 and 10, Beam, III et al disclose a method of fabricating a heterostructure, the method comprising:
growing epitaxially a first semiconductor layer 23 of the heterostructure, the first semiconductor layer comprising a III-nitride semiconductor material, the first semiconductor layer being supported by a substrate 20 [see Fig. 1; see also paragraph 0070, wherein the first semiconductor layer is comprised of epitaxial AlN]; and
after growing the first semiconductor layer, growing epitaxially a second semiconductor layer 38 of the heterostructure such that the second semiconductor layer is supported by the first semiconductor layer, the second semiconductor layer comprising a quaternary or higher order III-nitride alloy [see Fig. 2; see also paragraph 0024, wherein the quaternary or higher order III-nitride alloy is ScAlGaN],
wherein:
the quaternary or higher order III-nitride alloy comprises a group IIIB element [see paragraph 0024].
Beam, III et al do not disclose wherein growing the second semiconductor layer is implemented at least partially in a metal-rich environment. One such as Cuomo et al disclose growing epitaxially a similar semiconductor layer in a gallium-rich or indium-rich environment [see Figs. 1 and 2; see also paragraphs 0081-0084 and 0096]. It would have been obvious to one of ordinary skill in the art at the time of invention to grow epitaxially the second semiconductor layer in a metal-rich environment, in order to promote columnar growth of group III nitrides.
Claims 2, 3 and 9-11 are rejected under 35 U.S.C. 103 as being unpatentable over Leone et al (US Patent Application Publication 2021/0066070) in view of Cuomo et al (US Patent Application Publication 2002/0078881).
Regarding claims 2 and 3, Leone et al disclose the method of claim 1. Leone et al do not disclose wherein growing epitaxially the second semiconductor layer is implemented in a metal-rich environment. One such as Cuomo et al disclose growing epitaxially a similar semiconductor layer in a gallium-rich or indium-rich environment [see Figs. 1 and 2; see also paragraphs 0081-0084 and 0096]. It would have been obvious to one of ordinary skill in the art at the time of invention to grow epitaxially the second semiconductor layer in a metal-rich environment, in order to promote columnar growth of group III nitrides.
Regarding claims 9 and 10, Leone et al disclose a method of fabricating a heterostructure, the method comprising:
growing epitaxially a first semiconductor layer 16 of the heterostructure, the first semiconductor layer comprising a III-nitride semiconductor material, the first semiconductor layer being supported by a substrate 14 [see Fig. 2; see also paragraph 0023, wherein the first semiconductor layer is comprised of epitaxial AlN]; and
after growing the first semiconductor layer, growing epitaxially a second semiconductor layer 24 of the heterostructure such that the second semiconductor layer is supported by the first semiconductor layer, the second semiconductor layer comprising a quaternary or higher order III-nitride alloy [see Fig. 1; see also paragraph 0070, wherein the quaternary or higher order III-nitride alloy is AlScN],
wherein:
the quaternary or higher order III-nitride alloy comprises a group IIIB element [see paragraph 0070].
Leone et al do not disclose wherein growing the second semiconductor layer is implemented at least partially in a metal-rich environment. One such as Cuomo et al disclose growing epitaxially a similar semiconductor layer in a gallium-rich or indium-rich environment [see Figs. 1 and 2; see also paragraphs 0081-0084 and 0096]. It would have been obvious to one of ordinary skill in the art at the time of invention to grow epitaxially the second semiconductor layer in a metal-rich environment, in order to promote columnar growth of group III nitrides.
Regarding claim 11, the prior art of Leone et al and Cuomo et al disclose the method of claim 9. Furthermore, Leone et al disclose wherein growing the second semiconductor layer is implemented without removal of the substrate from the growth chamber after growth of the first semiconductor layer [see paragraphs 0066-0070, 0079 and 0098].
Claims 2, 3, 9,10, 12 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Hardy et al (US Patent Application Publication 2018/0130883) in view of Cuomo et al (US Patent Application Publication 2002/0078881).
Regarding claims 2 and 3, Hardy et al disclose the method of claim 1. Hardy et al do not disclose wherein growing epitaxially the second semiconductor layer is implemented in a metal-rich environment. One such as Cuomo et al disclose growing epitaxially a similar semiconductor layer in a gallium-rich or indium-rich environment [see Figs. 1 and 2; see also paragraphs 0081-0084 and 0096]. It would have been obvious to one of ordinary skill in the art at the time of invention to grow epitaxially the second semiconductor layer in a metal-rich environment, in order to promote columnar growth of group III nitrides.
Regarding claims 9 and 10, Leone et al disclose a method of fabricating a heterostructure, the method comprising:
growing epitaxially a first semiconductor layer 202 of the heterostructure, the first semiconductor layer comprising a III-nitride semiconductor material, the first semiconductor layer being supported by a substrate 201 [see Fig. 2; see also paragraph 0034]; and
after growing the first semiconductor layer, growing epitaxially a second semiconductor layer 203 of the heterostructure such that the second semiconductor layer is supported by the first semiconductor layer, the second semiconductor layer comprising a quaternary or higher order III-nitride alloy [see Fig. 2; see also paragraph 0035, wherein the quaternary or higher order III-nitride alloy is ScAlN],
wherein:
the quaternary or higher order III-nitride alloy comprises a group IIIB element [see paragraph 0035].
Hardy et al do not disclose wherein growing the second semiconductor layer is implemented at least partially in a metal-rich environment. One such as Cuomo et al disclose growing epitaxially a similar semiconductor layer in a gallium-rich or indium-rich environment [see Figs. 1 and 2; see also paragraphs 0081-0084 and 0096]. It would have been obvious to one of ordinary skill in the art at the time of invention to grow epitaxially the second semiconductor layer in a metal-rich environment, in order to promote columnar growth of group III nitrides.
Regarding claim 12, the prior art of Hardy et al and Cuomo et al disclose the method of claim 9. Furthermore, Hardy et al disclose wherein growing epitaxially the second semiconductor layer comprises adjusting a IIIB element/metal flux ratio during epitaxial growth of the second semiconductor layer [see paragraphs 0033-0037].
Regarding claim 13, the prior art of Hardy et al and Cuomo et al disclose the method of claim 9. Furthermore, Hardy et al disclose wherein the IIIB element/metal ratio is a scandium/aluminum flux ratio [see paragraph 0033-0037].
Allowable Subject Matter
Claims 15, 24 and 25 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: regarding dependent claim 15, the prior art of record fails to teach or make reasonably obvious, in combination with the other claimed elements and with sufficient specificity, wherein the terraced surface comprises a plurality of atomic steps; regarding dependent claims 24 and 25, the prior art of record fails to teach or make reasonably obvious, in combination with the other claimed elements and with sufficient specificity, comprising a channel layer supported by the barrier layer, or disposed between the buffer layer and the barrier layer, and comprising a compound semiconductor material, wherein the terraced surface is proximate to the channel layer.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to COLLEEN E SNOW whose telephone number is (571)272-8603. The examiner can normally be reached M-W, 8am-4:30pm.
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/C.E.S./Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899
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