DETAILED ACTION
This Notice is responsive to communication filed on 08/31/2026.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species 1, reading on Fig. 1 and Fig. 15 in the reply filed on 08/31/2026 is acknowledged.
Claims 6, 9-12, and 17-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 08/31/2026.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement filed 04/22/2024 fails to comply with the provisions of 37 CFR 1.97, 1.98 and MPEP § 609 because a copy of the Non Patent Literature "Journal of the Surface Finishing Society of Japan" has not been provided. It has been placed in the application file, but the information referred to therein has not been considered as to the merits. Applicant is advised that the date of any re-submission of any item of information contained in this information disclosure statement or the submission of any missing element(s) will be the date of submission for purposes of determining compliance with the requirements based on the time of filing the statement, including all certification requirements for statements under 37 CFR 1.97(e). See MPEP § 609.05(a).
The information disclosure statement (IDS) submitted on 11/14/2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-4, 7, and 13-16 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Murata et al. (WO 2020/026851) (see US 20210273017 for English translation and cited paragraphs).
Regarding claim 1, Murata discloses a solid-state imaging device comprising:
a pixel section Fig. 1: 110A that includes
a transparent semiconductor Fig. 1: 21 formed in an effective pixel region Fig. 1: 110A of an insulator Fig. 1: 29,
an organic photoelectric conversion film Fig. 1: 24 formed on the transparent semiconductor Fig. 1: 21 on a side opposite to the insulator Fig. 1: 29, and
a transparent electrode Fig. 1: 25+26 formed on the organic photoelectric conversion film Fig. 1: 24 on a side opposite to the transparent semiconductor Fig. 1: 21;
a coupling section disposed in the insulator Fig. 1: 29 in a peripheral region Fig. 1: 110B around the effective pixel region Fig. 1: 110A,
the coupling section being coupled to a circuit that supplies electricity to the transparent electrode Fig. 1: 25+26 (see para. 0063); and
a wiring line Fig. 1: 26 (see annotated Fig. 1 below) that electrically couples the transparent electrode Fig. 1: 25+26 and the coupling section to each other (para. 0079), and is formed by a transparent electrode material (para. 0080 teaches ITO material which is a transparent electrode material, and can be used as a wiring line).
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Regarding claim 2, Murata discloses the solid-state imaging device according to claim 1, wherein a thickness of the wiring line (Fig. 1: 26 portion annotated above) is thinner than a thickness of the transparent electrode Fig. 1: 25+26 (combined thickness of electrode 25 and layer 26).
Regarding claim 3, Murata discloses the solid-state imaging device according to claim 1, wherein the transparent electrode Fig. 1: 25+26 includes a first transparent electrode Fig. 1: 25 formed on the organic photoelectric conversion film Fig. 1: 24, and a second transparent electrode Fig. 1: 26 (portion above the photoelectric conversion film) formed on the first transparent electrode Fig. 1: 25 on a side opposite to the organic photoelectric conversion film Fig. 1: 24.
Regarding claim 4, Murata discloses the solid-state imaging device according to claim 3, wherein the wiring line (annotated above) is formed in same electrically-conductive layer as at least a portion of the transparent electrode Fig. 1: 25+26 (Fig. 1 shows layer 26 above the photoelectric conversion film is of the same electrically conductive layer as layer 26 in the peripheral region, annotated as the wiring line).
Regarding claim 7, Murata discloses the solid-state imaging device according to claim 1, wherein a protective film Fig. 1: 51+53 that covers the transparent electrode Fig. 1: 25+26 and the wiring line (annotated above) is formed in the effective pixel region Fig. 1: 110A and the peripheral region Fig. 1: 110B, and a light-blocking film Fig. 1: 54 that blocks light is formed on the protective film Fig. 1: 51+53 on a side opposite to the wiring line in the peripheral region Fig. 1: 110B (shown in Fig. 1).
Regarding claim 13, Murata discloses the solid-state imaging device according to claim 1, wherein the transparent semiconductor Fig. 1: 21 comprises IGZO (para. 0071).
Regarding claim 14, Murata discloses the solid-state imaging device according to claim 1, wherein the transparent electrode Fig. 1: 25+26 is formed by at least one transparent electrode material selected from IZO, ITO, SnOx, ZnOx, TiOx, CNT and Ag nanowires (para. 0079 teaches the layer 25 has a same material as layer 21 which comprises ITO (para. 0071), and para. 0080 teaches an ITO material for layer 26).
Regarding claim 15, Murata discloses the solid-state imaging device according to claim 1, wherein the wiring line (annotated above) is formed by same transparent electrode material as the transparent electrode Fig. 1: 25+26 or by a transparent electrode material different therefrom (annotated fig 1 shows the wiring line and a part of the transparent electrode are formed of the same layer/the same material).
Regarding claim 16, Murata discloses the solid-state imaging device according to claim 7, wherein the light- blocking film Fig. 1: 54 is a film having a lower stress than the protective film Fig. 1: 51+53.
The specification of the present application also teaches an Aluminum light blocking material, which has a low stress of 30MPa to 50MPa. Murata in para. 0088 teaches a material of the light blocking film 54 including Aluminum, which would result in the claimed property. The burden is upon the Applicant to prove otherwise. In re Fitzgerald, 619 F.2d 67, 205 USPQ 594 (CCPA 1980). Furthermore, according to MPEP § 2112.01 (I), "Where the claimed and prior art products are identical or substantially identical in structure or composition, or are produced by identical or substantially identical processes, a prima facie case of either anticipation or obviousness has been established". In re Best, 562F.2d 1252, 1255, 195 USPQ 430, 433 (CCPA 1977).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Rejection Note: Italicized claim limitations indicate limitations that are not explicitly disclosed in the primary reference(s).
Claims 5 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Murata et al. (WO 2020/026851) as applied to claim 1 above, and further in view of Takita et al. (US 20200035746).
Regarding claim 5, Muratta teaches the solid-state imaging device according to claim 1, comprising:
a sidewall insulator on a side surface of the organic photoelectric conversion film and on a side surface of the transparent semiconductor,
wherein the wiring line (annotated above) extends from the transparent electrode Fig. 1: 25+26 to the coupling section (towards the peripheral region Fig. 1: 110B) along the side surface of the organic photoelectric conversion film Fig. 1: 24 and the side surface of the transparent semiconductor Fig. 1: 21,
with the sidewall insulator being interposed therebetween.
Takita discloses the following claim limitations not explicitly disclosed by Muratta:
a sidewall insulator Fig. 5: 106b (see annotated portion below) on a side surface of the organic photoelectric conversion film Fig. 5: 15 and on a side surface of the transparent semiconductor Fig. 5: 14a (para. 0055),
with the sidewall insulator Fig. 5: 106b being interposed therebetween (shown in Fig. 4A).
It would be obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Muratta’s teachings with Takita’s in order to provide protective coverage of the photoelectric conversion layer and the lower electrode and to reduce permeation of moisture that is enters through flattening film (para. 0003, 0005).
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Regarding claim 8, Muratta teaches the solid-state imaging device according to claim 7, comprising:
a sidewall insulator on a side surface of the organic photoelectric conversion film and on a side surface of the transparent semiconductor,
wherein the wiring line (annotated above) extends from the transparent electrode Fig. 1: 25+26 to the coupling section (towards the peripheral region Fig. 1: 110B) along the side surface of the organic photoelectric conversion film Fig. 1: 24 and the side surface of the transparent semiconductor Fig. 1: 21,
with the sidewall insulator being interposed therebetween, and
the sidewall insulator extends between the insulator and the protective film in the peripheral region.
Takita discloses the following claim limitations not explicitly disclosed by Muratta:
a sidewall insulator Fig. 5: 106b (see annotated portion in claim 5 rejection) on a side surface of the organic photoelectric conversion film Fig. 5: 15 and on a side surface of the transparent semiconductor Fig. 5: 14a (para. 0055),
with the sidewall insulator Fig. 5: 106b being interposed therebetween (shown in Fig. 4A), and
the sidewall insulator Fig. 5: 106b extends between the insulator Fig. 5: 105 and the protective film Fig. 5: 111 in the peripheral region (shown in Fig. 5).
It would be obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Muratta’s teachings with Takita’s in order to provide protective coverage of the photoelectric conversion layer and the lower electrode and to reduce permeation of moisture that is enters through flattening film (para. 0003, 0005).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NKECHINYERE ESIABA whose telephone number is (571)272-0720. The examiner can normally be reached Monday - Friday 10am-5pm EST.
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/Nkechinyere Esiaba/Examiner, Art Unit 2817 /NICHOLAS J TOBERGTE/Primary Examiner, Art Unit 2817
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