DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-4, 7-8, and 15 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by US 2022/0102398 to Kim et al. (hereinafter Kim).
With respect to claim 1, Kim discloses a semiconductor device (e.g., image sensor capable of reducing an electric field concentration, see the annotated Fig. 11 below) (Kim, Figs. 1-12, ¶0004-¶0007, ¶0026-¶0101), comprising:
a semiconductor substrate (100) (Kim, Figs. 5, 7, 11, ¶0053-¶0056, ¶0088); and
a transistor (e.g., transfer transistor TX) (Kim, Figs. 5, 7, 11, ¶0063-¶0064) provided on the semiconductor substrate (100), wherein
a gate electrode (TG) (Kim, Figs. 5, 7, 10-11, ¶0063-¶0064) of the transistor (TX) includes:
a first part (e.g., a buried part VP) (Kim, Figs. 5, 7, 10-11, ¶0064, ¶0083) disposed at a position opposing the semiconductor substrate (100) via a gate insulating film (GI) of the transistor (TX) and configured to form a channel on the semiconductor substrate (100), and
a second part (e.g., protruding part PP) positioned on top of the first part (VP) and configured to have a smaller contribution (e.g., the second part PP has smaller thickness t2 than that t1 of the first part VP) (Kim, Figs. 5, 7, 10-11, ¶0083) toward the formation of the channel than the first part,
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the first part (VP) includes
a gate end which (e.g., a gate end of the buried part VP in the gate trench) (Kim, Figs. 9, 11, ¶0084, ¶0095) is positioned on a side of one region (e.g., floating diffusion region FD connected to the drain of the transfer transistor TX) (Kim, Fig. 2, ¶0032-¶0033) of a drain region and a source region of the transistor (TX) and in which an electric field concentrates with respect to the one region (e.g., electric field concentrated at a location where the transfer gate TG meets the floating diffusion region FD) (Kim, Figs. 5, 7, 9, 11, ¶0084), and
the gate end is positioned above (e.g., a bottom surface of the FD region) or below (e.g., a top surface of the FD region) a surface of the one region (e.g., FD) via a stepped portion (ST) (Kim, Figs. 5, 7, 9, 11, 21, ¶0095) provided on a side of a first surface (100a) of the semiconductor substrate (100) and is flush with a side surface of the second part (PP).
Regarding claim 2, Kim discloses the semiconductor device according to claim 1. Further, Kim discloses the semiconductor device, wherein the gate end (e.g., a gate end of the buried part VP in the gate trench) (Kim, Figs. 9, 11, ¶0084, ¶0095) is a corner portion (Kim, Fig. 9) which is positioned above the surface (e.g., the bottom surface of the FD region) of the one region (FD) via the stepped portion (ST).
Regarding claim 3, Kim discloses the semiconductor device according to claim 2. Further, Kim discloses the semiconductor device, wherein the transistor (TX) includes a side wall (GS) (Kim, Figs. 7, 11, ¶0064, ¶0096) configured to cover a side surface of the gate electrode (TG).
Regarding claim 4, Kim discloses the semiconductor device according to claim 3. Further, Kim discloses the semiconductor device, wherein the stepped portion (ST) (Kim, Figs. 7, 11, 21, 23, ¶0095, ¶0096) is positioned directly under the side wall (GS).
Regarding claim 7, Kim discloses the semiconductor device according to claim 12. Further, Kim discloses the semiconductor device, wherein the stepped portion (Kim, Figs. 7, 11, 17, 21, ¶0095) is positioned directly under the gate electrode (PP).
Regarding claim 8, Kim discloses the semiconductor device according to claim 1. Further, Kim discloses the semiconductor device, wherein the semiconductor substrate (100) is provided with a trench (RP1) (Kim, Figs. 7, 11, 17, 21, ¶0093-¶0095) which opens on a side of the first surface (100a), and at least a portion of the first part (VP) is disposed in the trench.
With respect to claim 15, Kim discloses an imaging apparatus (e.g., image sensor capable of reducing an electric field concentration, see the annotated Fig. 11 above) (Kim, Figs. 1-12, ¶0004-¶0007, ¶0026-¶0101) comprising:
a semiconductor substrate (100) (Kim, Figs. 2, 5, 7, 11, ¶0053-¶0056, ¶0088);
a sensor pixel (e.g., unit pixels PX) (Kim, Figs. 2, 5, 7, 11, ¶0032, ¶0055-¶0056) provided on the semiconductor substrate (100) and configured to perform photoelectric conversion, wherein
the sensor pixel (PX) includes:
a photoelectric conversion element (PD) (Kim, Figs. 2, 5, 7, 11, ¶0033, ¶0055-¶0056); and
a transfer transistor (e.g., transfer transistor TX) (Kim, Figs. 2, 5, 7, 11, ¶0032-¶0033, ¶0063-¶0064) electrically connected to the photoelectric conversion element (PD), and
a floating diffusion (FD) (Kim, Figs. 2, 5, 7, 11, ¶0032-¶0033, ¶0063-¶0064) configured to temporarily hold an electric charge output from the photoelectric conversion element (PD) via the transfer transistor (TX),
a gate electrode (TG) (Kim, Figs. 5, 7, 10-11, ¶0063-¶0064) of the transistor (TX) includes
a first part (e.g., a buried part VP) (Kim, Figs. 5, 7, 10-11, ¶0064, ¶0083) disposed at a position opposing the semiconductor substrate (100) via a gate insulating film (GI) of the transistor (TX) and configured to form a channel on the semiconductor substrate (100), and
a second part (e.g., protruding part PP) positioned on top of the first part (VP) and configured to have a smaller contribution (e.g., the second part PP has smaller thickness t2 than that t1 of the first part VP) (Kim, Figs. 5, 7, 10-11, ¶0083) toward the formation of the channel than the first part,
the first part (VP) includes
a gate end (e.g., a gate end of the buried part VP in the gate trench) (Kim, Figs. 9, 11, ¶0084, ¶0095) which is positioned on a side of the floating diffusion region (FD) and in which an electric field concentrates with respect to the floating diffusion region (FD) (e.g., electric field concentrated at a location where the transfer gate TG meets the floating diffusion region FD) (Kim, Figs. 5, 7, 9, 11, ¶0084), and
the gate end is positioned above a surface (e.g., a bottom surface of the FD region) of the floating diffusion region (FD) via a stepped portion (ST) (Kim, Figs. 5, 7, 9, 11, 21, ¶0095) provided on a side of a first surface (100a) of the semiconductor substrate (100) and is flush with a side surface of the second part (PP).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 5-6 are rejected under 35 U.S.C. 103 as being unpatentable over US 2022/0102398 to Kim.
Regarding claims 5 and 6, Kim discloses the semiconductor device according to claim 3. Further, Kim does not specifically disclose that a distance from an outer circumferential end of the side wall to the stepped portion is 10% or more of a width of the side wall (as claimed in claim 5); wherein a height of the stepped portion is 20% or more and 100% or less of the width of the side wall (as claimed in claim 6).
However, Kim teaches that the first part (e.g., the buried part VP) (Kim, Figs. 7, 9, 11, 21, ¶0084, ¶0095) of the gate (TG) has a sidewall which is positioned at a location in contact with the floating diffusion region FD and is spaced apart at a spacing distance DS from a sidewall of the second part (PP), to reduce an electric field concentration at a location where the transfer gate (TG) meets the floating diffusion region (FD); and the stepped portion (ST) is formed at the upper surface of the first part (VP), such that a distance from an outer circumferential end of the side wall to the second part (PP) corresponds to the spacing distance (DS), and a distance from an outer circumferential end of the side wall to the stepped portion formed at the upper surface of the first part (VP) depends on a shape of the first part (VP) of the transfer gate (TG).
Thus, Kim recognizes that a shape of the transfer gate and stepped portion at the upper surface of the buried gate part impacts an electric field concentration at a location where the transfer gate meets the floating diffusion region and thus operation of the device. Thus, a shape of the transfer gate and stepped portion at the upper surface of the buried gate part is a result-effective variable.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to vary, through routine optimization, the doping concentration of the doped layer as Kim has identified a shape of the transfer gate and stepped portion at the upper surface of the buried gate part as a result-effective variable. Further, a person of ordinary skill in the art would have had a reasonable expectation of success to arrive at a specific shape of the transfer gate and stepped portion to have a distance from an outer circumferential end of the side wall to the stepped portion is 10% or more of a width of the side wall (as claimed in claim 5); wherein a height of the stepped portion is 20% or more and 100% or less of the width of the side wall (as claimed in claim 6), in order to reduce an electric field concentration at a location where the transfer gate meets the floating diffusion region, and as taught by Kim (¶0004, ¶0084, ¶0095, ¶0101) (MPEP 2144.05).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Kim by optimizing a shape of the transfer gate and stepped portion at the upper surface of the buried gate part as taught by Kim to have the semiconductor device, wherein a distance from an outer circumferential end of the side wall to the stepped portion is 10% or more of a width of the side wall (as claimed in claim 5); wherein a height of the stepped portion is 20% or more and 100% or less of the width of the side wall (as claimed in claim 6), in order to reduce an electric field concentration at a location where the transfer gate meets the floating diffusion region, and thus to improve performance of the image sensor (Kim, ¶0004, ¶0084, ¶0095, ¶0101).
Claims 9-12 are rejected under 35 U.S.C. 103 as being unpatentable over US 2022/0102398 to Kim in view of Jin (US 2017/0069672).
Regarding claim 9, Kim discloses the semiconductor device according to claim 1. Further, Kim discloses the semiconductor device, wherein the gate end is positioned below the surface (e.g., the top surface of the FD) (Kim, Figs. 7, 9, 11, 21, ¶0084, ¶0095) of the one region (FD) via the stepped portion (ST), but does not specifically disclose that the first part is a conductor layer of a same first conductivity type as the source region and the drain region, the second part is a non-conductor layer or a conductor layer of a second conductivity type.
However, Jin teaches forming a transfer gate (TG) (Jin, Figs. 3, 8, 12, ¶0051-¶0054) including a first part (210) and the second part (230) having different conductivity types, to produce a drift field in the semiconductor substrate region (130) adjacent to the first part (210) and the second part (230) to allow the electrons to be moved to the floating diffusion region at an increased speed, and without being captured under the transfer gate. In Jin, the floating diffusion region (FD) adjacent to the transfer gate (TG) has the same conductivity type as the first part (Jin, Figs. 3, 8, 12, ¶0057).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Kim by forming the transfer gate including a first part and the second part having different conductivity types as taught by Jin to have the semiconductor device, wherein the first part is a conductor layer of a same first conductivity type as the source region and the drain region, the second part is a conductor layer of a second conductivity type, to produce a drift field in the semiconductor substrate region adjacent to the first part and the second part to allow the electrons to be moved to the floating diffusion region at an increased speed, and without being captured under the transfer gate (Jin, ¶0005-¶0006, ¶0053-¶0054, ¶0057, ¶0085-¶0086).
Regarding claim 10, Kim in view of Jin discloses the semiconductor device according to claim 9. Further, Kim discloses the semiconductor device, wherein the semiconductor substrate (100) is provided with a trench (RP1) (Kim, Figs. 7, 11, 17, 21, ¶0093-¶0095) which opens on a side of the first surface (100a), the stepped portion (ST) is present at an opening end of the trench (RP1), but does not specifically disclose that a boundary between the first part and the second part is positioned inside the trench.
However, Jin teaches forming a transfer gate (TG) (Jin, Figs. 3, 8, 12, ¶0051-¶0054, ¶0076) including a first part (210) and the second part (230) having different conductivity types, wherein a boundary between the first part (210) and the second part (230) is positioned inside the trench, to produce a drift field in the semiconductor substrate region (130) adjacent to the first part (210) and the second part (230) to allow the electrons to be moved along the side surfaces of the transfer gate (TG) to the floating diffusion region at an increased speed.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Kim/Jin by forming the transfer gate including a first part and the second part having different conductivity types as taught by Jin to have the semiconductor device, wherein a boundary between the first part and the second part is positioned inside the trench, to produce a drift field in the semiconductor substrate region adjacent to the first part and the second part to allow the electrons to be moved along the side surfaces of the transfer gate to the floating diffusion region at an increased speed (Jin, ¶0005-¶0006, ¶0053-¶0054, ¶0057, ¶0076, ¶0085-¶0086).
Regarding claims 11 and 12, Kim in view of Jin discloses the semiconductor device according to claim 9. Further, Kim does not specifically disclose the semiconductor device, wherein the gate electrode further includes a third part of a second conductivity type which is disposed on an opposite side to the first part across the second part (as claimed in claim 11); wherein at least a portion of the third part is positioned above the first surface of the semiconductor substrate (as claimed in claim 12).
However, Jin teaches forming a transfer gate (TG) (Jin, Fig. 8, ¶0051-¶0054, ¶0077) including a first part (210), the second part (220), and the third pard (230), wherein the third part and the first part (210) have different conductivity types, the second part prevents/reduces the electrons/holes from being diffused from one of the first part (210) and the third part (230), to produce a drift field in the semiconductor substrate region (130) adjacent to the first part (210) and the third part (230) to allow the electrons to be moved along the side surfaces of the transfer gate (TG) to the floating diffusion region at an increased speed. Further, Jin teaches an embodiment of Figs. 11-12, wherein at least a portion of the third part (e.g., an upper portion of the gate 230) (Jin, Figs. 11-12, ¶0081-¶0082) is positioned above the first surface of the semiconductor substrate (100).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Kim/Jin by forming the transfer gate including a first part and the third part having different conductivity types as taught by Jin to have the semiconductor device, wherein the gate electrode further includes a third part of a second conductivity type which is disposed on an opposite side to the first part across the second part (as claimed in claim 11); wherein at least a portion of the third part is positioned above the first surface of the semiconductor substrate (as claimed in claim 12), to produce a drift field in the semiconductor substrate region adjacent to the first part and the second part to allow the electrons to be moved along the side surfaces of the transfer gate to the floating diffusion region at an increased speed (Jin, ¶0005-¶0006, ¶0053-¶0054, ¶0057, ¶0081-¶0082, ¶0085-¶0086).
Claims 13 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over US 2022/0102398 to Kim in view of Jin (US 2017/0069672) as applied to claim 9, and further in view of Oh et al. (US 2015/0243693, hereinafter Oh).
Regarding claims 13 and 14, Kim in view of Jin discloses the semiconductor device according to claim 9. Further, Kim discloses the semiconductor device, further comprising a contact electrode (205) (Kim, Figs. 7, 11, ¶0068, ¶0099) which extends from the side of the first surface (100a) of the semiconductor substrate (100), and which connects (e.g., through the second part PP) to the first part (VP), but does not specifically disclose the semiconductor device, further comprising a contact electrode which extends to inside the semiconductor substrate (as claimed in claim 13); wherein the contact electrode penetrates the second part and connects to the first part (as claimed in claim 14).
However, Oh teaches forming an image sensor comprising a contact electrode (165) (Oh, Fig. 3C, ¶0043-¶0046) which extends to inside the semiconductor substrate (100) and connected to the transfer gate electrode (120) inside the trench, wherein the contact electrode (165) penetrates the upper part of the trench and connects to the first part (120), to produce highly integrated image sensor with reduced image lag.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Kim/Jin by forming a contact electrode to the transfer gate inside the gate trench as taught by Oh to have the semiconductor device, further comprising a contact electrode which extends to inside the semiconductor substrate (as claimed in claim 13); wherein the contact electrode penetrates the second part and connects to the first part (as claimed in claim 14), to produce highly integrated image sensor with reduced image lag (Oh, ¶0007, ¶0046-¶0047).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NATALIA GONDARENKO whose telephone number is (571)272-2284. The examiner can normally be reached 9:30 AM-7:30 PM.
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/NATALIA A GONDARENKO/Primary Examiner, Art Unit 2891
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