DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
The restriction requirement between different species, as set forth in the Office action mailed on 5/15/2026, is hereby withdrawn.
Status of claims
Claims 20-30 are pending in this application.
Information Disclosure Statement
Acknowledgement is made of Applicant's Information Disclosure Statement (IDS) from PTO-1449. The IDS has been considered.
Drawings
Fig. 1 should be designated by a legend such as --Prior Art-- because only that which is old is illustrated. See MPEP § 608.02(g). Corrected drawings in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. The replacement sheet(s) should be labeled “Replacement Sheet” in the page header (as per 37 CFR 1.84(c)) so as not to obstruct any portion of the drawing figures. If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
The drawings in Figs. 4E and 5A are objected to as failing to comply with 37 CFR 1.84(p)(4) because reference characters "60" have been used to designate quantum well intermixed areas and should be labelled “35” as shown in Fig. 4C. The label “60” is later used for solder material in Figs. 6-7. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The disclosure is objected to because of the following informalities:
In para [0061], line 5, Examiner believes that “the quantum well intermixed areas” should be indicated as “35” and not “60”, label “60” was already used for solder material in para [0045].
In para [0064], line 5, Examiner believes that “the quantum well intermixed areas” should be indicated as “35” and not “60”, for same reason as above.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim 20-21, 25-26 and 30 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Feix et al. (DE 102019126506 A1, citations from machine translated document, attached along with this office action).
Re Claim 20, Feix teaches a method for processing an optoelectronic device, the method comprising:
providing a functional semiconductor layer stack (31+33+35, Fig. 1, paras [0057] – [0060]) on a growth substrate (growth substrate 2, Fig. 1, para [0057]) having an active layer (33, Fig. 1, para [0058]) for emitting light arranged between a first doped layer (31 is n-doped, Fig. 1, para [0057]) and a second doped layer (35, note that 35 is part of layer 32, which is p-doped, para [0059]), the second doped layer having a thickness (thickness of 35, Fig. 1);
depositing a hard mask (layer 34 acts as masking layer, Fig. 1, para [0062]) on the second doped layer (35, Fig. 1);
structuring the hard mask (patterning the layer 34, Fig. 2, para [0062]) as to expose surface areas of the second doped layer (35, Fig. 2, para [0062]), wherein the exposed surface areas are recessed (openings 50, Fig. 2, para [0061]) with regard to a surface of the second doped layer beneath remaining portions of the hard mask (see Fig. 2) and a remaining thickness of a material of the second doped layer at the exposed surface areas is less than 600 nm (after the recess formation, the remaining thickness of the layer 35 can be between 300 nm and 600 nm, para [0061]);
diffusing a dopant (diffusion of zinc, para [0063]) into the material of the second doped layer at the exposed surface areas (see Fig. 3) as to perform a quantum well intermixing within regions of the active layer beneath the exposed surface areas (see Fig. 3, paras [0063] – [0065]); and
applying a first contact material (42, Fig. 4, para [0069]) at least on unexposed areas of the doped second layer (35, see Fig. 4),
wherein diffusing the dopant (diffusion of zinc, para [0063]) comprises:
depositing Zn as a dopant on the exposed surface areas at a first temperature (deposition of zinc layer at a first temperature, few nm thick, para [0063]), and
diffusing the dopant into material of the second doped layer and into regions of the active layer beneath the exposed surface areas at a second temperature, the second temperature being higher than the first temperature (diffusion of zinc into the semiconductor layers and the active layer at a second elevated temperature of approximately 550 °C, para [0064]).
Re Claim 21, Feix teaches the method according to claim 20, wherein diffusing the dopant comprises a directed deposition of the dopant onto the exposed surface areas (diffusion of zinc directly via a gaseous precursor, paras [0063] – [0064]).
Re Claim 25, Feix teaches the method according to claim 20, wherein depositing the active layer (33, Fig. 1, para [0058]) comprises depositing a plurality of alternating quantum well layers (61, Fig. 1, para [0058]) and quantum barrier layers (62, Fig. 1, para [0058]).
Re Claim 26, Feix teaches the method according to claim 25, wherein the quantum barrier layers comprise InGaAlP or InGaAIN (para [0060]) with an aluminum content between 50% and 100 %, inclusive (Al content can be greater than 60% in quantum barrier layers, para [0060]), and wherein the quantum well layers comprise InGaAlP or InGaAIN (para [0060]) with an aluminum content between 0% and 40 %, inclusive (Al content can be between 10% and 30% in quantum well layers, para [0060]).
Re Claim 30, Feix teaches the method according to claim 20, further comprising, after removing the growth substrate at least partially (removal of growth substrate 2, Fig. 5), applying a second contact material (41, Fig. 5, para [0070]) on the first doped layer (31, Fig. 5).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 23 is rejected under 35 U.S.C. 103 as being unpatentable over Feix et al. (DE 102019126506 A1, citations from machine translated document, attached along with this office action), and further in view of Kwon et al. (US 2014/0328363 A1).
Re Claim 23, Feix teaches the method according to claim 20, wherein structuring the hard mask (patterning of layer 34, Fig. 2) comprises:
depositing a photoresist layer on the hard mask (deposition of an additional photoresist layer on top of masking layer 34, para [0062]).
Feix does not explicitly state the following:
structuring the photoresist layer and removing portions of the photoresist layer; and
removing the exposed portions of the hard mask (34, Fig. 3) and the material of the second doped layer (35, Fig. 3) by an etching process.
Related semiconductor art Kwon teaches a similar patterning process (Fig. 4) where the photoresist (166, Fig. 4) is patterned using a photolithography process (para [0041]) and the materials from the mask layer (165, Fig. 4) are removed via an etching process (para [0041]).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, to modify the method of Feix, such that the photoresist layer is patterned via a photolithography process followed by removal of the exposed portions of the hard mask and the material of the second doped layer via an etching process as disclosed by Kwon. The selection of a known processes for patterning and etching for their known purposes of removing materials in a controlled manner is prima facie obvious. Also see KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385, 1395-97 (2007).
Claims 24 and 27-29 are rejected under 35 U.S.C. 103 as being unpatentable over Feix et al. (DE 102019126506 A1, citations from machine translated document, attached along with this office action), and further in view of Bour et al. (US 2017/0170360 A1).
Re Claim 24, Feix teaches the method according to claim 20, wherein providing the functional semiconductor layer stack (31+33+35, Fig. 1) on the growth substrate (2, Fig. 1) comprises:
providing the growth substrate (2, Fig. 1),
depositing the first doped layer (31, Fig. 1, paras [0056] – [0057]),
depositing the active layer (33, Fig. 1, paras [0058]), and
depositing the second doped layer (35, note that 35 is part of layer 32, Fig. 1, para [0059]) on the active layer.
Feix does not teach a current distribution layer between the growth substrate and the first doped layer.
However, related semiconductor art Bour, teaches a current spreading layer (104, Fig. 1A, para [0082]) between the growth substrate (102, Fig. 1A, para [0083]) and the first doped layer (106, Fig. 1A, para [0082]).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, to include a current distribution later between the growth substrate and the first doped layer into the method of Feix, as disclosed by Bour, because the additional current distribution layer ensures uniform distribution of the electrical current, thus improving the electrical performance of the light emitting device, while also enhancing overall efficiency.
Re Claim 27, Feix teaches the method according to claim 20, further comprising:
removing the growth substrate at least partially (removal of growth substrate 2, compare Figs. 4 and 5); and
mesa structuring the functional semiconductor layer stack (forming mesa regions 39, Fig. 4, para [0067]) to form cavities (separation trenches 8, Fig. 4, para [0067]) in the material of the functional semiconductor layer stack between two unexposed areas (see Fig. 4),
wherein quantum well intermixed areas are located at edges of sidewalls (intermixed areas 51 are on the edges of the sidewalls, Fig. 4, para [0068]).
Feix does not show the detailed methods on how the LED in Fig. 5 is formed from the step in Fig. 4, and hence does not teach rebonding the functional semiconductor layer stack by arranging the first contact material on a temporary substrate. One of ordinary skill would look into related arts to teach the detailed steps involved in isolating the LED.
Related art Bour teaches the detailed steps involved in isolating a fully functional LED from the initial semiconductor stacks (Figs. 1A - 2). For example, the step of Fig. 4 in Feix is equivalent to the step in Fig. 1C of Bour, which has the growth substrate (102, Fig. 1C, para [0087]), the semiconductor stack (115, Figs. 1A-1C, paras [0081] – [0082]) and the first contact (116, Figs. 1B-1C, para [0086]). Following the step in Fig. 1C, a temporary substrate (130, Fig. 1D, para [0087]) is attached which helps in isolating the LED, as recited in the claim limitation.
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, to incorporate the detailed steps in isolating a single LED into the method of Feix, which includes rebonding the functional semiconductor layer stack by arranging the first contact material on a temporary substrate, as taught by Bour. The use of known art-recognized processing steps for its known purpose of isolating a functional LED is prima facie obvious. Also see KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385, 1395-97 (2007).
Re Claim 28, Feix modified by Bour teaches the method according to claim 27, but does not disclose that the sidewalls are tapered in a direction of the temporary substrate.
However, related art Bour teaches that the sidewalls of the semiconductor stack of the isolated LED regions can be straight (Fig. 1D) or can be tapered in a direction of the temporary substrate (130, Fig. 9E).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, to substitute the straight sidewall with a tapered sidewall, as they are both art-recognized alternate structure depending on the design choice of the LED, and does not affect its performance. The substitution of a known sidewall structure for its known purpose of LED design is prima facie obvious. Also see KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385, 1395-97 (2007).
Re Claim 29, Feix modified by Bour teaches the method according to claim 27, wherein rebonding comprises depositing a sacrificial layer (130, Fig. 1D, Bour) at least partially on the first contact material (116, Figs. 1B-1D, Bour) so that a pillar of a temporary substrate material (pillars 132, Fig. 1D-1E, para [0087], Bour) is formed supporting the functional semiconductor layer stack (see Fig. 1D-1E, Bour).
Allowable Subject Matter
Claim 22 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for allowable subject matter:
Re Claim 22, Feix teaches that diffusing the dopant (Zn diffusion, para [0063]) comprises depositing the dopant onto sidewalls of the unexposed areas of the second doped layer (deposition of zinc layer, few nm thick, inside the recess 50, which comprises sidewalls of unexposed second doped layer 35, Fig. 3, para [0063]). However, Feix fails to teach that the “a material deposited on the sidewalls is less thick than a material deposited on the exposed surface areas”. This limitation is neither anticipated nor made obvious by the prior art of record in the Examiner’s opinion, when taken in context of the entire claim 22 and in view of the independent claim 20, as a whole.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
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/P.D./Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
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