Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-6, 10-15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yoneda (US 20210043671 A1).
Regarding claim 1, Yoneda discloses a light detection apparatus (Fig. 9; [0131]: “detects the light”), comprising:
a sensor substrate (100) that includes a first semiconductor substrate (243) on which a plurality of photoelectric converters (FD. Note: “plurality” is shown at least by Fig. 1A, which shows the pluralization of 331, and Fig. 1B shows 331 includes FD) is arranged; and
a logic substrate (101) that includes:
a second semiconductor substrate (211) to which a logic circuit ([0051]: “control”; schematically illustrated in Fig. 1B) is provided; and
a first wiring layer (352) that is stacked on the second semiconductor substrate, the sensor substrate and the logic substrate being arranged in a layered formation (100/101 are directly “layered”) such that the first wiring layer of the logic substrate faces (layer 352 “faces” towards substrate 100) the sensor substrate,
wherein a second wiring layer (270/271) that includes a wiring (270) and an insulator (271) is formed inside of the second semiconductor substrate (270/271 each pass full through substrate 211, and are thus “formed inside”), the wiring and the insulator being arranged inside a trench ([0121]: “provided in an opening formed in the semiconductor substrate 211”) formed in the second semiconductor substrate, the wiring extending in parallel (wiring 270 extends in a plurality of directions and at least one of these directions is “parallel with a first surface”. See dashed reference lines for “extending” directions) with a first surface (See annotated figure for surface designation) that is a surface of the second semiconductor substrate that is situated on a side of the first wiring layer, and the insulator insulating the wiring from the second semiconductor substrate (insulator 271 fully insulates wiring 270 from substrate 211; [0121]: “insulating layer”), and
wherein the wiring in the second wiring layer is electrically connected to a specified portion (See annotated figure for portion designation) of a connection target (“connection target” is being designated here as transistor 106) formed in the first surface of the second semiconductor substrate or (Note: the alternative “or” is not being selected for this interpretation of the reference) a second surface (See annotated figure for surface designation) of the second semiconductor substrate that is situated opposite to the first surface.
Illustrated below is a marked and annotated figure of Fig. 9 of Yoneda.
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Regarding claim 2, Yoneda discloses the light detection apparatus according to claim 1 (Fig. 9), wherein the wiring in the second wiring layer has a larger cross-sectional area (as measured between dashed reference lines A and C, See annotated figure) in a width direction (Vertical Direction) than wiring situated in the first wiring layer (a portion of 352, as measured between dashed reference lines A and C, See annotated figure).
Although not relied upon for this rejection, the examiner has also considered guidance from the following portions of MPEP, and noted them here for clarity of the record, and to promote compact prosecution: MPEP 2144.04 (IV): Changes in Size/Proportion: “where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device…the claimed device was not patentably distinct from the prior art device”; MPEP 2144.04 (IV): Changes in Shape: Dailey.
Regarding claim 3, Yoneda discloses the light detection apparatus according to claim 1 (Fig. 9), wherein the wiring in the second wiring layer is power supply wiring ([0124]: “the source and the drain of the transistor 106 can be electrically connected to…the driver circuit”) that applies a power supply voltage to the connection target ([0124]: “driver circuit”).
Regarding claim 4, Yoneda discloses the light detection apparatus according to claim 1 (Fig. 9), wherein the wiring in the second wiring layer is electrically connected to the specified portion through a connection conductor (a portion of 352, See annotated figure for conductor designation. Note: an alternative interpretation of this claim is designating annotated portions “Connection Conductor”, “Wiring”, and “Conductor” as the “connection conductor”. This alternative interpretation is used in the rejection of dependent claim 6.) that extends (this conductor extends in multiple directions including the vertical direction which is relied upon here) in parallel with a direction of a thickness of the second semiconductor substrate (the vertical direction is relied upon here).
Regarding claim 5, Yoneda discloses the light detection apparatus according to claim 4 (Fig. 9), wherein
the wiring in the second wiring layer is electrically connected to the specified portion through a first connection conductor (See annotated figure, annotated as “Connection Conductor”), wiring situated in the first wiring layer (See annotated figure, designated as “wiring”), and a second connection conductor (See annotated figure, designated as “conductor”), the first connection conductor being the connection conductor extending in parallel with the thickness direction toward the wiring in the first wiring layer from the wiring in the second wiring layer (this is the same designated conductor as in claim 4), the second connection conductor extending (this conductor extends in multiple directions including the vertical direction which is relied upon here) in parallel with the thickness direction toward the specified portion from the wiring in the first wiring layer, or
the wiring in the second wiring layer is electrically connected to the specified portion through a first connection conductor, wiring situated in a third wiring layer that is formed on the second surface, and a second connection conductor, the first connection conductor being the connection conductor extending in parallel with the thickness direction toward the wiring in the third wiring layer from the wiring in the second wiring layer, the second connection conductor extending in parallel with the thickness direction toward the specified portion from the wiring in the third wiring layer.
Regarding claim 6, Yoneda discloses the light detection apparatus according to claim 4 (Fig. 9), wherein the wiring in the second wiring layer is directly electrically connected to the specified portion only through the connection conductor (Note: the alternative interpretation of the reference noted in the claim 4 rejection is relied upon here.) that extends (this conductor extends in multiple directions including the vertical direction which is relied upon here) from the wiring in the second wiring layer toward the specified portion situated in the second semiconductor substrate in parallel with the direction of the thickness of the second semiconductor substrate.
Regarding independent claim 10, Yoneda discloses an electronic apparatus (Fig. 1A), comprising: a light detection apparatus (Fig. 9; [0131]: “detects the light”) comprising:
a sensor substrate (100) that includes a first semiconductor substrate (243) on which a plurality of photoelectric converters (FD. Note: “plurality” is shown at least by Fig. 1A, which shows the pluralization of 331, and Fig. 1B shows 331 includes FD) is arranged, and
a logic substrate (101) that includes
a second semiconductor substrate (211) to which a logic circuit ([0051]: “control”; schematically illustrated in Fig. 1B) is provided and
a first wiring layer (352) that is stacked on the second semiconductor substrate, the sensor substrate and the logic substrate being arranged in a layered formation (100/101 are directly “layered”) such that the first wiring layer of the logic substrate faces (layer 352 “faces” towards substrate 100) the sensor substrate,
wherein a second wiring layer (270/271) that includes a wiring (270) and an insulator (271) is formed inside of the second semiconductor substrate (270/271 each pass full through substrate 211, and are thus “formed inside”), the wiring and the insulator being arranged inside a trench ([0121]: “provided in an opening formed in the semiconductor substrate 211”) formed in the second semiconductor substrate, the wiring extending in parallel (wiring 270 extends in a plurality of directions and at least one of these directions is “parallel with a first surface”. See dashed reference lines for “extending” directions) with a first surface (See annotated figure for surface designation) that is a surface of the second semiconductor substrate that is situated on a side of the first wiring layer, and the insulator insulating the wiring from the second semiconductor substrate (insulator 271 fully insulates wiring 270 from substrate 211; [0121]: “insulating layer”), and
wherein the wiring in the second wiring layer is electrically connected to a specified portion (See annotated figure for portion designation) of a connection target (“connection target” is being designated here as transistor 106) formed in the first surface of the second semiconductor substrate or (Note: the alternative “or” is not being selected for this interpretation of the reference) a second surface (See annotated figure for surface designation) a second surface of the second semiconductor substrate that is situated opposite to the first surface.
Regarding claim 11, Yoneda discloses the electronic apparatus according to claim 10 (Fig. 9), wherein the wiring in the second wiring layer has a larger cross-sectional area (as measured between dashed reference lines A and C, See annotated figure) in a width direction (Vertical Direction) than wiring situated in the first wiring layer (a portion of 352, as measured between dashed reference lines A and C, See annotated figure).
Although not relied upon for this rejection, the examiner has also considered guidance from the following portions of MPEP, and noted them here for clarity of the record, and to promote compact prosecution: MPEP 2144.04 (IV): Changes in Size/Proportion: “where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device…the claimed device was not patentably distinct from the prior art device”; MPEP 2144.04 (IV): Changes in Shape: Dailey.
Regarding claim 12, Yoneda discloses the electronic apparatus according to claim 10 (Fig. 9), wherein the wiring in the second wiring layer is power supply wiring ([0124]: “the source and the drain of the transistor 106 can be electrically connected to…the driver circuit”) that applies a power supply voltage to the connection target ([0124]: “driver circuit”).
Regarding claim 13, Yoneda discloses the electronic apparatus according to claim 10 (Fig. 9), wherein the wiring in the second wiring layer is electrically connected to the specified portion through a connection conductor (a portion of 352, See annotated figure for conductor designation. Note: an alternative interpretation of this claim is designating annotated portions “Connection Conductor”, “Wiring”, and “Conductor” as the “connection conductor”. This alternative interpretation is used in the rejection of dependent claim 15.) that extends (this conductor extends in multiple directions including the vertical direction which is relied upon here) in parallel with a direction of a thickness of the second semiconductor substrate (the vertical direction is relied upon here).
Regarding claim 14, Yoneda discloses the electronic apparatus according to claim 13 (Fig. 9), wherein
the wiring in the second wiring layer is electrically connected to the specified portion through a first connection conductor (See annotated figure, annotated as “Connection Conductor”), wiring situated in the first wiring layer (See annotated figure, designated as “wiring”), and a second connection conductor (See annotated figure, designated as “conductor”), the first connection conductor being the connection conductor extending in parallel with the thickness direction toward the wiring in the first wiring layer from the wiring in the second wiring layer (this is the same designated conductor as in claim 4), the second connection conductor extending (this conductor extends in multiple directions including the vertical direction which is relied upon here) in parallel with the thickness direction toward the specified portion from the wiring in the first wiring layer, or
the wiring in the second wiring layer is electrically connected to the specified portion through a first connection conductor, wiring situated in a third wiring layer that is formed on the second surface, and a second connection conductor, the first connection conductor being the connection conductor extending in parallel with the thickness direction toward the wiring in the third wiring layer from the wiring in the second wiring layer, the second connection conductor extending in parallel with the thickness direction toward the specified portion from the wiring in the third wiring layer.
Regarding claim 15, Yoneda discloses the electronic apparatus according to claim 13 (Fig. 9), wherein the wiring in the second wiring layer is directly electrically connected to the specified portion only through the connection conductor (Note: the alternative interpretation of the reference noted in the claim 4 rejection is relied upon here.) that extends (this conductor extends in multiple directions including the vertical direction which is relied upon here) from the wiring in the second wiring layer toward the specified portion situated in the second semiconductor substrate in parallel with the direction of the thickness of the second semiconductor substrate.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Rejection Note: Italicized claim limitations indicate limitations that are not explicitly disclosed in the primary reference (or combination of references), but are disclosed or rendered obvious by secondary references or remarks.
Claims 8-9 are rejected under 35 U.S.C. 103 as being unpatentable over Yoneda as applied to claim 1 above, and further in view of Lin (US 20210050300 A1).
Regarding claim 8, Yoneda discloses the light detection apparatus according to claim 1 (Fig. 9), but fails to teach specific materials used for “the insulator”. Thus, Yoneda fails to teach “wherein a material of the insulator is at least one of silicon oxide, silicon nitride, silicon oxynitride, or carbon-containing silicon oxide”.
Lin discloses wherein a material of the insulator (Fig. 34B: 153) is at least one of silicon oxide ([0662]: “silicon oxide”), silicon nitride, silicon oxynitride, or carbon-containing silicon oxide.
A person having ordinary skill in the art before the effective filing date would have had a reasonable expectation of success choosing from the finite number of identified predictable solutions for “a material of the insulator” (from Lin) for “the insulator” (of Yoneda), because in each situation the insulator is used in the same situation (Yoneda: [0122]: “a through-silicon via”; Lin: [0662]: “through silicon vias”). These predictable solutions include “silicon oxide” as this may be chosen from a finite number of identified, predictable solutions (Lin: [0662]). Absent unexpected results, it would have been obvious to one having ordinary skill in the art before the effective filing date to try using a different material for “the insulator”. Therefore, the claim would have been obvious to one of ordinary skill in the art before the effective filing date because “a person of ordinary skill has good reason to pursue the known options within his or her technique grasp. If this leads to the anticipated success, it is likely the product not of innovation but of ordinary skill and common sense.” MPEP 2143 (1)(E).
Illustrated below is Fig. 34B of Lin.
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Regarding claim 9, Yoneda discloses the light detection apparatus according to claim 1 (Fig. 9), but fails to teach specific materials used for “the wiring”. Thus, Yoneda fails to teach “wherein a material of the wiring is at least one of tungsten, titanium, tantalum, cobalt, or aluminum”.
Lin discloses wherein a material of the wiring (Fig. 34B: 154/155/156) is at least one of tungsten, titanium ([0662]: “titanium”), tantalum, cobalt, or aluminum.
A person having ordinary skill in the art before the effective filing date would have had a reasonable expectation of success choosing from the finite number of identified predictable solutions for “a material of the wiring” (from Lin) for “the wiring” (of Yoneda), because in each situation the wiring is used in the same situation (Yoneda: [0122]: “a through-silicon via”; Lin: [0662]: “through silicon vias”). These predictable solutions include “titanium” as this may be chosen from a finite number of identified, predictable solutions (Lin: [0662]). Absent unexpected results, it would have been obvious to one having ordinary skill in the art before the effective filing date to try using a different material for “the wiring”. Therefore, the claim would have been obvious to one of ordinary skill in the art before the effective filing date because “a person of ordinary skill has good reason to pursue the known options within his or her technique grasp. If this leads to the anticipated success, it is likely the product not of innovation but of ordinary skill and common sense.” MPEP 2143 (1)(E).
Claims 17-18 are rejected under 35 U.S.C. 103 as being unpatentable over Yoneda as applied to claim 10 above, and further in view of Lin.
Regarding claim 17, Yoneda discloses the light detection apparatus according to claim 10 (Fig. 9), but fails to teach specific materials used for “the insulator”. Thus, Yoneda fails to teach “wherein a material of the insulator is at least one of silicon oxide, silicon nitride, silicon oxynitride, or carbon-containing silicon oxide”.
Lin discloses wherein a material of the insulator (153) is at least one of silicon oxide ([0662]: “silicon oxide”), silicon nitride, silicon oxynitride, or carbon-containing silicon oxide.
A person having ordinary skill in the art before the effective filing date would have had a reasonable expectation of success choosing from the finite number of identified predictable solutions for “a material of the insulator” (from Lin) for “the insulator” (of Yoneda), because in each situation the insulator is used in the same situation (Yoneda: [0122]: “a through-silicon via”; Lin: [0662]: “through silicon vias”). These predictable solutions include “silicon oxide” as this may be chosen from a finite number of identified, predictable solutions (Lin: [0662]). Absent unexpected results, it would have been obvious to one having ordinary skill in the art before the effective filing date to try using a different material for “the insulator”. Therefore, the claim would have been obvious to one of ordinary skill in the art before the effective filing date because “a person of ordinary skill has good reason to pursue the known options within his or her technique grasp. If this leads to the anticipated success, it is likely the product not of innovation but of ordinary skill and common sense.” MPEP 2143 (1)(E).
Regarding claim 18, Yoneda discloses the light detection apparatus according to claim 10 (Fig. 9), but fails to teach specific materials used for “the wiring”. Thus, Yoneda fails to teach “wherein a material of the wiring is at least one of tungsten, titanium, tantalum, cobalt, or aluminum”.
Lin discloses wherein a material of the wiring (154/155/156) is at least one of tungsten, titanium ([0662]: “titanium”), tantalum, cobalt, or aluminum.
A person having ordinary skill in the art before the effective filing date would have had a reasonable expectation of success choosing from the finite number of identified predictable solutions for “a material of the wiring” (from Lin) for “the wiring” (of Yoneda), because in each situation the wiring is used in the same situation (Yoneda: [0122]: “a through-silicon via”; Lin: [0662]: “through silicon vias”). These predictable solutions include “titanium” as this may be chosen from a finite number of identified, predictable solutions (Lin: [0662]). Absent unexpected results, it would have been obvious to one having ordinary skill in the art before the effective filing date to try using a different material for “the wiring”. Therefore, the claim would have been obvious to one of ordinary skill in the art before the effective filing date because “a person of ordinary skill has good reason to pursue the known options within his or her technique grasp. If this leads to the anticipated success, it is likely the product not of innovation but of ordinary skill and common sense.” MPEP 2143 (1)(E).
Claims 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Yoneda.
Regarding claim 19, Yoneda discloses the electronic apparatus according to claim 10, but only illustrates a single wiring as “the wiring in the second wiring layer”. Thus, Yoneda fails to explicitly teach “wherein the wiring in the second wiring layer includes a first wiring and a second wiring, the first wiring and the second wiring being arranged inside of the second semiconductor substrate and being insulated from the second semiconductor substrate by the insulator”.
Nevertheless, Yoneda teaches: 1) “the wiring in the second wiring substrate” corresponds to a unit of the apparatus (Fig. 9: unit FD); and 2) teaches the apparatus includes a plurality duplicated units (Fig. 1A: duplicated units 331; Fig. 1B: unit 331 includes FD). A person of ordinary skill in the art before the effective filing date would have had a reasonable expectation of success incorporating “the first wiring” and “the second wiring” as duplicated wirings because as cited above, Yoneda teaches “the first wiring” and teaches duplicating the structures related to “the first wiring”. Doing so would arrive at the claimed wiring configuration. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have the claimed wiring configuration because it is a duplication of parts encompassed by the teachings of the prior art. MPEP 2144.04 (VI)(B).
Regarding claim 20, Yoneda discloses the electronic apparatus according to claim 1, but only illustrates a single wiring as “the wiring in the second wiring layer”. Thus, Yoneda fails to explicitly teach “wherein the wiring in the second wiring layer includes a first wiring and a second wiring, the first wiring and the second wiring being arranged inside of the second semiconductor substrate and being insulated from the second semiconductor substrate by the insulator”.
Nevertheless, Yoneda teaches: 1) “the wiring in the second wiring substrate” corresponds to a unit of the apparatus (Fig. 9: unit FD); and 2) teaches the apparatus includes a plurality duplicated units (Fig. 1A: duplicated units 331; Fig. 1B: unit 331 includes FD). A person of ordinary skill in the art before the effective filing date would have had a reasonable expectation of success incorporating “the first wiring” and “the second wiring” as duplicated wirings because as cited above, Yoneda teaches “the first wiring” and teaches duplicating the structures related to “the first wiring”. Doing so would arrive at the claimed wiring configuration. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have the claimed wiring configuration because it is a duplication of parts encompassed by the teachings of the prior art. MPEP 2144.04 (VI)(B).
Allowable Subject Matter
Claims 7 and 16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The primary reason for the allowable subject matter of claim 7 is the inclusion of the limitation “wherein the second wiring layer is a multilayered wiring layer in which a plurality of pieces of wiring are spaced in a layered formation in the direction of the thickness of the second semiconductor substrate, and a piece of wiring in an upper layer and a piece of wiring in a lower layer are connected to each other through a via” in combination with the other limitations in the claim. For example, prior art of record fails to teach or be reasonably combined to render obvious the claimed limitations “pieces of wiring”, “connected to each other through a via”, “trench”, in combination with all other structural and electrical configuration requirements and limitations in claims 7 and 1.
The primary reason for the allowable subject matter of claim 16 is the inclusion of the limitation “wherein the second wiring layer is a multilayered wiring layer in which a plurality of pieces of wiring are spaced in a layered formation in the direction of the thickness of the second semiconductor substrate, and a piece of wiring in an upper layer and a piece of wiring in a lower layer are connected to each other through a via” in combination with the other limitations in the claim. For example, prior art of record fails to teach or be reasonably combined to render obvious the claimed limitations “pieces of wiring”, “connected to each other through a via”, “trench”, in combination with all other structural and electrical configuration requirements and limitations in claims 16 and 10.
Response to Arguments
Applicant's arguments filed 9/23/2026 have been fully considered but they are not persuasive.
Applicant argues:
Applicant argues with respect to amended claim 1 that “Kamei fails to disclose, teach or suggest “the wiring and the insulator being arranged inside a trench formed in the second semiconductor substrate” as claimed…Claim 10 contains similar limitations…”. Remarks at pg. 3.
Examiner’s reply:
Applicant’s arguments with respect to claim(s) 1 and 10 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. The examiner notes the new grounds of rejection raised in the instant Office action have been necessitated by Applicant’s amendments, which have changed the scope of the claims beyond that which had previously been considered.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to WILLIAM H ANDERSON whose telephone number is (571)272-2534. The examiner can normally be reached Monday-Friday, 8:00-5:00.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kretelia Graham can be reached at (571) 272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/WILLIAM H ANDERSON/ Primary Examiner, Art Unit 2817
